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[Qemu-devel] [PULL 06/10] cputlb: Merge tlb_flush_nocheck into tlb_flush
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 06/10] cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_work |
Date: |
Wed, 31 Oct 2018 12:21:15 +0000 |
The difference between the two sets of APIs is now miniscule.
This allows tlb_flush, tlb_flush_all_cpus, and tlb_flush_all_cpus_synced
to be merged with their corresponding by_mmuidx functions as well. For
accounting, consider mmu_idx_bitmask = ALL_MMUIDX_BITS to be a full flush.
Tested-by: Emilio G. Cota <address@hidden>
Reviewed-by: Emilio G. Cota <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
accel/tcg/cputlb.c | 93 +++++++++++-----------------------------------
1 file changed, 21 insertions(+), 72 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2cd3886fd6..a3a417e81a 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -122,75 +122,6 @@ static void tlb_flush_one_mmuidx_locked(CPUArchState *env,
int mmu_idx)
env->tlb_d[mmu_idx].vindex = 0;
}
-/* This is OK because CPU architectures generally permit an
- * implementation to drop entries from the TLB at any time, so
- * flushing more entries than required is only an efficiency issue,
- * not a correctness issue.
- */
-static void tlb_flush_nocheck(CPUState *cpu)
-{
- CPUArchState *env = cpu->env_ptr;
- int mmu_idx;
-
- assert_cpu_is_self(cpu);
- atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1);
- tlb_debug("(count: %zu)\n", tlb_flush_count());
-
- /*
- * tlb_table/tlb_v_table updates from any thread must hold tlb_c.lock.
- * However, updates from the owner thread (as is the case here; see the
- * above assert_cpu_is_self) do not need atomic_set because all reads
- * that do not hold the lock are performed by the same owner thread.
- */
- qemu_spin_lock(&env->tlb_c.lock);
- env->tlb_c.pending_flush = 0;
- for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
- tlb_flush_one_mmuidx_locked(env, mmu_idx);
- }
- qemu_spin_unlock(&env->tlb_c.lock);
-
- cpu_tb_jmp_cache_clear(cpu);
-}
-
-static void tlb_flush_global_async_work(CPUState *cpu, run_on_cpu_data data)
-{
- tlb_flush_nocheck(cpu);
-}
-
-void tlb_flush(CPUState *cpu)
-{
- if (cpu->created && !qemu_cpu_is_self(cpu)) {
- CPUArchState *env = cpu->env_ptr;
- uint16_t pending;
-
- qemu_spin_lock(&env->tlb_c.lock);
- pending = env->tlb_c.pending_flush;
- env->tlb_c.pending_flush = ALL_MMUIDX_BITS;
- qemu_spin_unlock(&env->tlb_c.lock);
-
- if (pending != ALL_MMUIDX_BITS) {
- async_run_on_cpu(cpu, tlb_flush_global_async_work,
- RUN_ON_CPU_NULL);
- }
- } else {
- tlb_flush_nocheck(cpu);
- }
-}
-
-void tlb_flush_all_cpus(CPUState *src_cpu)
-{
- const run_on_cpu_func fn = tlb_flush_global_async_work;
- flush_all_helper(src_cpu, fn, RUN_ON_CPU_NULL);
- fn(src_cpu, RUN_ON_CPU_NULL);
-}
-
-void tlb_flush_all_cpus_synced(CPUState *src_cpu)
-{
- const run_on_cpu_func fn = tlb_flush_global_async_work;
- flush_all_helper(src_cpu, fn, RUN_ON_CPU_NULL);
- async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_NULL);
-}
-
static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
{
CPUArchState *env = cpu->env_ptr;
@@ -212,13 +143,17 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu,
run_on_cpu_data data)
qemu_spin_unlock(&env->tlb_c.lock);
cpu_tb_jmp_cache_clear(cpu);
+
+ if (mmu_idx_bitmask == ALL_MMUIDX_BITS) {
+ atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1);
+ }
}
void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
{
tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap);
- if (!qemu_cpu_is_self(cpu)) {
+ if (cpu->created && !qemu_cpu_is_self(cpu)) {
CPUArchState *env = cpu->env_ptr;
uint16_t pending, to_clean;
@@ -238,6 +173,11 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
}
}
+void tlb_flush(CPUState *cpu)
+{
+ tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS);
+}
+
void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu, uint16_t idxmap)
{
const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work;
@@ -248,8 +188,12 @@ void tlb_flush_by_mmuidx_all_cpus(CPUState *src_cpu,
uint16_t idxmap)
fn(src_cpu, RUN_ON_CPU_HOST_INT(idxmap));
}
-void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
- uint16_t idxmap)
+void tlb_flush_all_cpus(CPUState *src_cpu)
+{
+ tlb_flush_by_mmuidx_all_cpus(src_cpu, ALL_MMUIDX_BITS);
+}
+
+void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxmap)
{
const run_on_cpu_func fn = tlb_flush_by_mmuidx_async_work;
@@ -259,6 +203,11 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
async_safe_run_on_cpu(src_cpu, fn, RUN_ON_CPU_HOST_INT(idxmap));
}
+void tlb_flush_all_cpus_synced(CPUState *src_cpu)
+{
+ tlb_flush_by_mmuidx_all_cpus_synced(src_cpu, ALL_MMUIDX_BITS);
+}
+
static inline bool tlb_hit_page_anyprot(CPUTLBEntry *tlb_entry,
target_ulong page)
{
--
2.17.2
- [Qemu-devel] [PULL 00/10] cputlb: track dirty tlbs and general cleanup, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 01/10] cputlb: Move tlb_lock to CPUTLBCommon, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 02/10] cputlb: Remove tcg_enabled hack from tlb_flush_nocheck, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 03/10] cputlb: Move cpu->pending_tlb_flush to env->tlb_c.pending_flush, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 07/10] cputlb: Merge tlb_flush_page into tlb_flush_page_by_mmuidx, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 06/10] cputlb: Merge tlb_flush_nocheck into tlb_flush_by_mmuidx_async_work,
Richard Henderson <=
- [Qemu-devel] [PULL 09/10] cputlb: Filter flushes on already clean tlbs, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 04/10] cputlb: Split large page tracking per mmu_idx, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 08/10] cputlb: Count "partial" and "elided" tlb flushes, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 05/10] cputlb: Move env->vtlb_index to env->tlb_d.vindex, Richard Henderson, 2018/10/31
- [Qemu-devel] [PULL 10/10] cputlb: Remove tlb_c.pending_flushes, Richard Henderson, 2018/10/31