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[Qemu-devel] [PULL 08/10] target/arm: Conditionalize some asserts on aar
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/10] target/arm: Conditionalize some asserts on aarch32 support |
Date: |
Fri, 2 Nov 2018 17:16:36 +0000 |
From: Richard Henderson <address@hidden>
When populating id registers from kvm, on a host that doesn't support
aarch32 mode at all, neither arm_div nor jazelle will be supported either.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 5 +++++
target/arm/cpu.c | 15 +++++++++++++--
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 8e6779936eb..b5eff79f73b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3296,6 +3296,11 @@ static inline bool isar_feature_aa64_fp16(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
}
+static inline bool isar_feature_aa64_aa32(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL0) >= 2;
+}
+
static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 8f16e96b6c8..784a4c2dfcc 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -774,6 +774,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
CPUARMState *env = &cpu->env;
int pagebits;
Error *local_err = NULL;
+ bool no_aa32 = false;
/* If we needed to query the host kernel for the CPU features
* then it's possible that might have failed in the initfn, but
@@ -820,6 +821,16 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
set_feature(env, ARM_FEATURE_V7VE);
}
}
+
+ /*
+ * There exist AArch64 cpus without AArch32 support. When KVM
+ * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
+ * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
+ */
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
+ no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
+ }
+
if (arm_feature(env, ARM_FEATURE_V7VE)) {
/* v7 Virtualization Extensions. In real hardware this implies
* EL2 and also the presence of the Security Extensions.
@@ -829,7 +840,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
* Presence of EL2 itself is ARM_FEATURE_EL2, and of the
* Security Extensions is ARM_FEATURE_EL3.
*/
- assert(cpu_isar_feature(arm_div, cpu));
+ assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
set_feature(env, ARM_FEATURE_LPAE);
set_feature(env, ARM_FEATURE_V7);
}
@@ -855,7 +866,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
if (arm_feature(env, ARM_FEATURE_V6)) {
set_feature(env, ARM_FEATURE_V5);
if (!arm_feature(env, ARM_FEATURE_M)) {
- assert(cpu_isar_feature(jazelle, cpu));
+ assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
set_feature(env, ARM_FEATURE_AUXCR);
}
}
--
2.19.1
- [Qemu-devel] [PULL v3 00/10] target-arm queue, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 10/10] hw/arm: versal: Add a virtual Xilinx Versal board, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 08/10] target/arm: Conditionalize some asserts on aarch32 support,
Peter Maydell <=
- [Qemu-devel] [PULL 09/10] hw/arm: versal: Add a model of Xilinx Versal SoC, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 07/10] hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 06/10] strongarm: mask off high[31:28] bits from dir and state registers, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 05/10] MAINTAINERS: Remove bouncing email in ARM ACPI, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 04/10] tests/boot-serial-test: Add microbit board testcase, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 03/10] hw/arm/nrf51_soc: Connect UART to nRF51 SoC, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 01/10] hw/arm/virt: Set VIRT_COMPAT_3_0 compat, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 02/10] hw/char: Implement nRF51 SoC UART, Peter Maydell, 2018/11/02
- Re: [Qemu-devel] [PULL v3 00/10] target-arm queue, Peter Maydell, 2018/11/02