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[Qemu-devel] [PULL 06/10] strongarm: mask off high[31:28] bits from dir
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 06/10] strongarm: mask off high[31:28] bits from dir and state registers |
Date: |
Fri, 2 Nov 2018 17:16:34 +0000 |
From: Prasad J Pandit <address@hidden>
The high[31:28] bits of 'direction' and 'state' registers of
SA-1100/SA-1110 device are reserved. Setting them may lead to
OOB 's->handler[]' array access issue. Mask off [31:28] bits to
avoid it.
Reported-by: Moguofang <address@hidden>
Signed-off-by: Prasad J Pandit <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/strongarm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index ec2627374d0..644a9c45b4e 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -587,12 +587,12 @@ static void strongarm_gpio_write(void *opaque, hwaddr
offset,
switch (offset) {
case GPDR: /* GPIO Pin-Direction registers */
- s->dir = value;
+ s->dir = value & 0x0fffffff;
strongarm_gpio_handler_update(s);
break;
case GPSR: /* GPIO Pin-Output Set registers */
- s->olevel |= value;
+ s->olevel |= value & 0x0fffffff;
strongarm_gpio_handler_update(s);
break;
--
2.19.1
- [Qemu-devel] [PULL v3 00/10] target-arm queue, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 10/10] hw/arm: versal: Add a virtual Xilinx Versal board, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 08/10] target/arm: Conditionalize some asserts on aarch32 support, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 09/10] hw/arm: versal: Add a model of Xilinx Versal SoC, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 07/10] hw/arm/xilinx_zynq: Use the ARRAY_SIZE macro, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 06/10] strongarm: mask off high[31:28] bits from dir and state registers,
Peter Maydell <=
- [Qemu-devel] [PULL 05/10] MAINTAINERS: Remove bouncing email in ARM ACPI, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 04/10] tests/boot-serial-test: Add microbit board testcase, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 03/10] hw/arm/nrf51_soc: Connect UART to nRF51 SoC, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 01/10] hw/arm/virt: Set VIRT_COMPAT_3_0 compat, Peter Maydell, 2018/11/02
- [Qemu-devel] [PULL 02/10] hw/char: Implement nRF51 SoC UART, Peter Maydell, 2018/11/02
- Re: [Qemu-devel] [PULL v3 00/10] target-arm queue, Peter Maydell, 2018/11/02