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[Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction |
Date: |
Mon, 14 Jan 2019 12:11:16 +1100 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 60865945e4..911d6f06b3 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2696,7 +2696,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
* +-----+-------+---+---+-------+---+-------+-------+------+------+
*
* opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
- * LDPSW 01
+ * LDPSW/STGP 01
* LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
* V: 0 -> GPR, 1 -> Vector
* idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
@@ -2721,6 +2721,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
bool is_signed = false;
bool postindex = false;
bool wback = false;
+ bool set_tag = false;
TCGv_i64 clean_addr, dirty_addr;
@@ -2733,6 +2734,14 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
if (is_vector) {
size = 2 + opc;
+ } else if (opc == 1 && !is_load) {
+ /* STGP */
+ if (!dc_isar_feature(aa64_mte_insn_reg, s) || index == 0) {
+ unallocated_encoding(s);
+ return;
+ }
+ size = 3;
+ set_tag = true;
} else {
size = 2 + extract32(opc, 1, 1);
is_signed = extract32(opc, 0, 1);
@@ -2783,7 +2792,12 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
if (!postindex) {
tcg_gen_addi_i64(dirty_addr, dirty_addr, offset);
}
- clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
+ if (set_tag) {
+ clean_addr = new_tmp_a64(s);
+ gen_helper_stg(clean_addr, cpu_env, dirty_addr);
+ } else {
+ clean_addr = clean_data_tbi(s, dirty_addr, rn == 31);
+ }
if (is_vector) {
if (is_load) {
--
2.17.2
- [Qemu-devel] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags, (continued)
- [Qemu-devel] [PATCH 01/17] target/arm: Add MTE_ACTIVE to tb_flags, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 02/17] target/arm: Extract TCMA with ARMVAParameters, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 03/17] target/arm: Add MTE system registers, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 04/17] target/arm: Fill in helper_mte_check, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 05/17] target/arm: Suppress tag check for sp+offset, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 06/17] target/arm: Implement the IRG instruction, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 07/17] target/arm: Implement ADDG, SUBG instructions, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 08/17] target/arm: Implement the GMI instruction, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 09/17] target/arm: Implement the SUBP instruction, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 10/17] target/arm: Implement LDG, STG, ST2G instructions, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 11/17] target/arm: Implement the STGP instruction,
Richard Henderson <=
- [Qemu-devel] [PATCH 12/17] target/arm: Implement the LDGV and STGV instructions, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 13/17] target/arm: Set PSTATE.TCO on exception entry, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 14/17] tcg: Introduce target-specific page data for user-only, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 16/17] target/arm: Enable MTE, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 15/17] target/arm: Add allocation tag storage for user-only, Richard Henderson, 2019/01/13
- [Qemu-devel] [PATCH 17/17] tests/tcg/aarch64: Add mte smoke tests, Richard Henderson, 2019/01/13