[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v1 5/8] RISC-V: Add priv_ver to DisasContext |
Date: |
Mon, 14 Jan 2019 23:58:32 +0000 |
The gen methods should access state from DisasContext. Add priv_ver
field to the DisasContext struct.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/translate.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0581b3c1f7..833adf1d6f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -43,6 +43,7 @@ typedef struct DisasContext {
DisasContextBase base;
/* pc_succ_insn points to the instruction following base.pc_next */
target_ulong pc_succ_insn;
+ target_ulong priv_ver;
uint32_t opcode;
uint32_t mstatus_fs;
uint32_t mem_idx;
@@ -1330,7 +1331,7 @@ static void gen_system(CPURISCVState *env, DisasContext
*ctx, uint32_t opc,
#ifndef CONFIG_USER_ONLY
/* Extract funct7 value and check whether it matches SFENCE.VMA */
if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) {
- if (env->priv_ver == PRIV_VERSION_1_10_0) {
+ if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
/* sfence.vma */
/* TODO: handle ASID specific fences */
gen_helper_tlb_flush(cpu_env);
@@ -1384,7 +1385,7 @@ static void gen_system(CPURISCVState *env, DisasContext
*ctx, uint32_t opc,
gen_helper_wfi(cpu_env);
break;
case 0x104: /* SFENCE.VM */
- if (env->priv_ver <= PRIV_VERSION_1_09_1) {
+ if (ctx->priv_ver <= PRIV_VERSION_1_09_1) {
gen_helper_tlb_flush(cpu_env);
} else {
gen_exception_illegal(ctx);
@@ -1851,13 +1852,15 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx)
}
}
-static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
+static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
*cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
+ CPURISCVState *env = cpu->env_ptr;
ctx->pc_succ_insn = ctx->base.pc_first;
ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
+ ctx->priv_ver = env->priv_ver;
ctx->frm = -1; /* unknown rounding mode */
}
--
2.19.1
[Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers, Alistair Francis, 2019/01/14
Re: [Qemu-devel] [PATCH v1 4/8] RISC-V: Use riscv prefix consistently on cpu helpers, Richard Henderson, 2019/01/15