[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for
From: |
Stefan Markovic |
Subject: |
Re: [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for 32 major CP0 registers |
Date: |
Thu, 17 Jan 2019 14:57:42 +0000 |
On 3.1.19. 17:34, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <address@hidden>
>
> Add preprocessor constants for 32 major CP0 registers.
>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> ---
> target/mips/cpu.h | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
Reviewed-by: Stefan Markovic <address@hidden>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 6c2a7e4..b095422 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -233,6 +233,38 @@ typedef struct mips_def_t mips_def_t;
> * 7 TagLo TagHi KScratch<n>
> *
> */
> +#define CPO_REGISTER_00 0
> +#define CPO_REGISTER_01 1
> +#define CPO_REGISTER_02 2
> +#define CPO_REGISTER_03 3
> +#define CPO_REGISTER_04 4
> +#define CPO_REGISTER_05 5
> +#define CPO_REGISTER_06 6
> +#define CPO_REGISTER_07 7
> +#define CPO_REGISTER_08 8
> +#define CPO_REGISTER_09 9
> +#define CPO_REGISTER_10 10
> +#define CPO_REGISTER_11 11
> +#define CPO_REGISTER_12 12
> +#define CPO_REGISTER_13 13
> +#define CPO_REGISTER_14 14
> +#define CPO_REGISTER_15 15
> +#define CPO_REGISTER_16 16
> +#define CPO_REGISTER_17 17
> +#define CPO_REGISTER_18 18
> +#define CPO_REGISTER_19 19
> +#define CPO_REGISTER_20 20
> +#define CPO_REGISTER_21 21
> +#define CPO_REGISTER_22 22
> +#define CPO_REGISTER_23 23
> +#define CPO_REGISTER_24 24
> +#define CPO_REGISTER_25 25
> +#define CPO_REGISTER_26 26
> +#define CPO_REGISTER_27 27
> +#define CPO_REGISTER_28 28
> +#define CPO_REGISTER_29 29
> +#define CPO_REGISTER_30 30
> +#define CPO_REGISTER_31 31
>
>
> typedef struct TCState TCState;
- [Qemu-devel] [PATCH 7/8] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, (continued)
- [Qemu-devel] [PATCH 7/8] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 5/8] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 1/8] target/mips: Move comment containing summary of CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/03
- Re: [Qemu-devel] [PATCH 2/8] target/mips: Add preprocessor constants for 32 major CP0 registers,
Stefan Markovic <=
- [Qemu-devel] [PATCH 3/8] target/mips: Use preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/03
- [Qemu-devel] [PATCH 4/8] target/mips: Add fields for SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/03
- Re: [Qemu-devel] [PATCH 0/8] target/mips: Update Inter-Thread Communication Unit support, no-reply, 2019/01/23