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[Qemu-devel] [PULL 02/12] target/mips: Add preprocessor constants for 32
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers |
Date: |
Thu, 17 Jan 2019 19:12:55 +0100 |
From: Aleksandar Markovic <address@hidden>
Add preprocessor constants for 32 major CP0 registers.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6c2a7e4..b095422 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,6 +233,38 @@ typedef struct mips_def_t mips_def_t;
* 7 TagLo TagHi KScratch<n>
*
*/
+#define CPO_REGISTER_00 0
+#define CPO_REGISTER_01 1
+#define CPO_REGISTER_02 2
+#define CPO_REGISTER_03 3
+#define CPO_REGISTER_04 4
+#define CPO_REGISTER_05 5
+#define CPO_REGISTER_06 6
+#define CPO_REGISTER_07 7
+#define CPO_REGISTER_08 8
+#define CPO_REGISTER_09 9
+#define CPO_REGISTER_10 10
+#define CPO_REGISTER_11 11
+#define CPO_REGISTER_12 12
+#define CPO_REGISTER_13 13
+#define CPO_REGISTER_14 14
+#define CPO_REGISTER_15 15
+#define CPO_REGISTER_16 16
+#define CPO_REGISTER_17 17
+#define CPO_REGISTER_18 18
+#define CPO_REGISTER_19 19
+#define CPO_REGISTER_20 20
+#define CPO_REGISTER_21 21
+#define CPO_REGISTER_22 22
+#define CPO_REGISTER_23 23
+#define CPO_REGISTER_24 24
+#define CPO_REGISTER_25 25
+#define CPO_REGISTER_26 26
+#define CPO_REGISTER_27 27
+#define CPO_REGISTER_28 28
+#define CPO_REGISTER_29 29
+#define CPO_REGISTER_30 30
+#define CPO_REGISTER_31 31
typedef struct TCState TCState;
--
2.7.4
- [Qemu-devel] [PULL 00/12] MIPS queue for January 17, 2019*, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 06/12] target/mips: Add field and R/W access to ITU control register ICR0, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 01/12] target/mips: Move comment containing summary of CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 08/12] target/mips: Update ITU to handle bus errors, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 10/12] target/mips: Add CP0 register MemoryMapID, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 12/12] target/mips: Introduce 32 R5900 multimedia registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 03/12] target/mips: Use preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 09/12] target/mips: Amend preprocessor constants for CP0 registers, Aleksandar Markovic, 2019/01/17