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[Qemu-devel] [PULL 04/12] target/mips: Add fields for SAARI and SAAR CP0
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers |
Date: |
Thu, 17 Jan 2019 19:12:57 +0100 |
From: Yongbok Kim <address@hidden>
Add fields for SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Yongbok Kim <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 10 ++++++++--
target/mips/machine.c | 6 ++++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b095422..1c2c682 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
* 3 BadInstrX
* 4 GuestCtl1 GuestCtl0Ext
* 5 GuestCtl2
- * 6 GuestCtl3
- * 7
+ * 6 SAARI GuestCtl3
+ * 7 SAAR
*
*
* Register 12 Register 13 Register 14 Register 15
@@ -546,6 +546,12 @@ struct CPUMIPSState {
* CP0 Register 9
*/
int32_t CP0_Count;
+ uint32_t CP0_SAARI;
+#define CP0SAARI_TARGET 0 /* 5..0 */
+ uint64_t CP0_SAAR[2];
+#define CP0SAAR_BASE 12 /* 43..12 */
+#define CP0SAAR_SIZE 1 /* 5..1 */
+#define CP0SAAR_EN 0
/*
* CP0 Register 10
*/
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 704e9c0..111d7c3 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 15,
- .minimum_version_id = 15,
+ .version_id = 16,
+ .minimum_version_id = 16,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
--
2.7.4
- [Qemu-devel] [PULL 00/12] MIPS queue for January 17, 2019*, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 06/12] target/mips: Add field and R/W access to ITU control register ICR0, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 01/12] target/mips: Move comment containing summary of CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 08/12] target/mips: Update ITU to handle bus errors, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 10/12] target/mips: Add CP0 register MemoryMapID, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 12/12] target/mips: Introduce 32 R5900 multimedia registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 03/12] target/mips: Use preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 09/12] target/mips: Amend preprocessor constants for CP0 registers, Aleksandar Markovic, 2019/01/17
- [Qemu-devel] [PULL 11/12] target/mips: Rename 'rn' to 'register_name', Aleksandar Markovic, 2019/01/17
- Re: [Qemu-devel] [PULL 00/12] MIPS queue for January 17, 2019*, Peter Maydell, 2019/01/18