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[Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0 |
Date: |
Fri, 18 Jan 2019 14:57:58 +0000 |
From: Aaron Lindsay <address@hidden>
This is immediately necessary for the PMUv3 implementation to check
ID_DFR0.PerfMon to enable/disable specific features, but defines the
full complement of fields for possible future use elsewhere.
Signed-off-by: Aaron Lindsay <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 964487d6863..79378df96e6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1681,6 +1681,15 @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
FIELD(ID_AA64MMFR1, XNX, 28, 4)
+FIELD(ID_DFR0, COPDBG, 0, 4)
+FIELD(ID_DFR0, COPSDBG, 4, 4)
+FIELD(ID_DFR0, MMAPDBG, 8, 4)
+FIELD(ID_DFR0, COPTRC, 12, 4)
+FIELD(ID_DFR0, MMAPTRC, 16, 4)
+FIELD(ID_DFR0, MPROFDBG, 20, 4)
+FIELD(ID_DFR0, PERFMON, 24, 4)
+FIELD(ID_DFR0, TRACEFILT, 28, 4)
+
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=
R_V7M_CSSELR_INDEX_MASK);
/* If adding a feature bit which corresponds to a Linux ELF
--
2.20.1
- [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac, (continued)
- [Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23], Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0,
Peter Maydell <=
- [Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial(), Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0, Peter Maydell, 2019/01/18
- [Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC, Peter Maydell, 2019/01/18
- Re: [Qemu-devel] [PULL 00/49] target-arm queue, no-reply, 2019/01/31