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[Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID |
Date: |
Fri, 18 Jan 2019 17:59:43 +0100 |
From: Aleksandar Markovic <address@hidden>
Add CP0 register MemoryMapID. Only data field is added.
The corresponding functionality will be added in future
patches.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 1 +
target/mips/machine.c | 5 +++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a5381b7..21daf50 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -536,6 +536,7 @@ struct CPUMIPSState {
*/
target_ulong CP0_Context;
target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+ int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
*/
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 111d7c3..1341ab1 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 16,
- .minimum_version_id = 16,
+ .version_id = 17,
+ .minimum_version_id = 17,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -253,6 +253,7 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
+ VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
--
2.7.4
- [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID,
Aleksandar Markovic <=
- [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 03/12] target/mips: Use preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name', Aleksandar Markovic, 2019/01/18
- Re: [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2, Peter Maydell, 2019/01/21