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Re: [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 |
Date: |
Mon, 21 Jan 2019 19:19:19 +0000 |
On Fri, 18 Jan 2019 at 16:59, Aleksandar Markovic
<address@hidden> wrote:
>
> From: Aleksandar Markovic <address@hidden>
>
> The following changes since commit 681d61362d3f766a00806b89d6581869041f73cb:
>
> Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request'
> into staging (2019-01-17 12:48:42 +0000)
>
> are available in the git repository at:
>
> https://github.com/AMarkovic/qemu tags/mips-queue-january-17-2019-v2
>
> for you to fetch changes up to a168a796e1c251787fcdf2d9ca1e9e69cb86ffcd:
>
> target/mips: Introduce 32 R5900 multimedia registers (2019-01-18 16:53:28
> +0100)
>
> ----------------------------------------------------------------
>
> MIPS queue for January 17, 2019 - v2
>
> v1->v2:
> - fixed "make check" error
>
> content:
> - provide access to configuration registers SAARI, SAAR, and
> MemoryMapID
> - update Inter-Thread Communication Unit
> - CP0-related cleanups
> - introduce R5900 multimedia registers
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.
-- PMM
- [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers, (continued)
- [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to SAARI and SAAR CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 03/12] target/mips: Use preprocessor constants for 32 major CP0 registers, Aleksandar Markovic, 2019/01/18
- [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name', Aleksandar Markovic, 2019/01/18
- Re: [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2,
Peter Maydell <=