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[Qemu-devel] [PULL 07/23] tcg/i386: Implement vector saturating arithmet
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 07/23] tcg/i386: Implement vector saturating arithmetic |
Date: |
Mon, 28 Jan 2019 07:58:51 -0800 |
Only MO_8 and MO_16 are implemented, since that's all the
instruction set provides.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.inc.c | 42 +++++++++++++++++++++++++++++++++++++++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 7bd7eae672..efbd5a6fc9 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -185,7 +185,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 1
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 6f4c16326f..a5791dfaa5 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -377,6 +377,10 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_PADDW (0xfd | P_EXT | P_DATA16)
#define OPC_PADDD (0xfe | P_EXT | P_DATA16)
#define OPC_PADDQ (0xd4 | P_EXT | P_DATA16)
+#define OPC_PADDSB (0xec | P_EXT | P_DATA16)
+#define OPC_PADDSW (0xed | P_EXT | P_DATA16)
+#define OPC_PADDUB (0xdc | P_EXT | P_DATA16)
+#define OPC_PADDUW (0xdd | P_EXT | P_DATA16)
#define OPC_PAND (0xdb | P_EXT | P_DATA16)
#define OPC_PANDN (0xdf | P_EXT | P_DATA16)
#define OPC_PBLENDW (0x0e | P_EXT3A | P_DATA16)
@@ -408,6 +412,10 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
#define OPC_PSUBW (0xf9 | P_EXT | P_DATA16)
#define OPC_PSUBD (0xfa | P_EXT | P_DATA16)
#define OPC_PSUBQ (0xfb | P_EXT | P_DATA16)
+#define OPC_PSUBSB (0xe8 | P_EXT | P_DATA16)
+#define OPC_PSUBSW (0xe9 | P_EXT | P_DATA16)
+#define OPC_PSUBUB (0xd8 | P_EXT | P_DATA16)
+#define OPC_PSUBUW (0xd9 | P_EXT | P_DATA16)
#define OPC_PUNPCKLBW (0x60 | P_EXT | P_DATA16)
#define OPC_PUNPCKLWD (0x61 | P_EXT | P_DATA16)
#define OPC_PUNPCKLDQ (0x62 | P_EXT | P_DATA16)
@@ -2591,9 +2599,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const add_insn[4] = {
OPC_PADDB, OPC_PADDW, OPC_PADDD, OPC_PADDQ
};
+ static int const ssadd_insn[4] = {
+ OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
+ };
+ static int const usadd_insn[4] = {
+ OPC_PADDSB, OPC_PADDSW, OPC_UD2, OPC_UD2
+ };
static int const sub_insn[4] = {
OPC_PSUBB, OPC_PSUBW, OPC_PSUBD, OPC_PSUBQ
};
+ static int const sssub_insn[4] = {
+ OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
+ };
+ static int const ussub_insn[4] = {
+ OPC_PSUBSB, OPC_PSUBSW, OPC_UD2, OPC_UD2
+ };
static int const mul_insn[4] = {
OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
};
@@ -2631,9 +2651,21 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_vec:
insn = add_insn[vece];
goto gen_simd;
+ case INDEX_op_ssadd_vec:
+ insn = ssadd_insn[vece];
+ goto gen_simd;
+ case INDEX_op_usadd_vec:
+ insn = usadd_insn[vece];
+ goto gen_simd;
case INDEX_op_sub_vec:
insn = sub_insn[vece];
goto gen_simd;
+ case INDEX_op_sssub_vec:
+ insn = sssub_insn[vece];
+ goto gen_simd;
+ case INDEX_op_ussub_vec:
+ insn = ussub_insn[vece];
+ goto gen_simd;
case INDEX_op_mul_vec:
insn = mul_insn[vece];
goto gen_simd;
@@ -3007,6 +3039,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_ussub_vec:
case INDEX_op_cmp_vec:
case INDEX_op_x86_shufps_vec:
case INDEX_op_x86_blend_vec:
@@ -3074,6 +3110,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type,
unsigned vece)
}
return 1;
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_ussub_vec:
+ return vece <= MO_16;
+
default:
return 0;
}
--
2.17.2
- [Qemu-devel] [PULL 00/23] tcg queued patches, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 01/23] tcg: Add logical simplifications during gvec expand, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 02/23] tcg: Add gvec expanders for nand, nor, eqv, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 03/23] tcg: Add write_aofs to GVecGen4, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 04/23] tcg: Add opcodes for vector saturated arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 05/23] tcg: Add opcodes for vector minmax arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 07/23] tcg/i386: Implement vector saturating arithmetic,
Richard Henderson <=
- [Qemu-devel] [PULL 08/23] tcg/i386: Implement vector minmax arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 06/23] tcg/i386: Split subroutines out of tcg_expand_vec_op, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 09/23] tcg/aarch64: Implement vector saturating arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 10/23] tcg/aarch64: Implement vector minmax arithmetic, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 22/23] tcg/tci: enable dynamic TLB sizing, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 11/23] cputlb: do not evict empty entries to the vtlb, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 15/23] tcg/ppc: enable dynamic TLB sizing, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 17/23] tcg/s390: enable dynamic TLB sizing, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 16/23] tcg/sparc: enable dynamic TLB sizing, Richard Henderson, 2019/01/28
- [Qemu-devel] [PULL 14/23] tcg/aarch64: enable dynamic TLB sizing, Richard Henderson, 2019/01/28