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From: | amagdy . afifi |
Subject: | [Qemu-devel] Add proper alignment check and pending 'C' extension for riscv |
Date: | Fri, 22 Feb 2019 18:25:54 +0200 |
Dear All, I'm submiting this patch to properly check the next instruction alignment and scheduale compression extenstion enable upon 'MISA' register writes to later aligned instruction through exporting next instruction 'pc' to riscv cpu state Thanks, Ahmed
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