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Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
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Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree |
Date: |
Wed, 27 Feb 2019 10:36:34 -0800 (PST) |
Patchew URL: https://patchew.org/QEMU/address@hidden/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: address@hidden
Subject: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
t [tag update] patchew/address@hidden -> patchew/address@hidden
Switched to a new branch 'test'
6ff2674d6d target/riscv: Remaining rvc insn reuse 32 bit translators
69cfc476d2 target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
a79d96ef4f target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e21ef3efe4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
ab13d11898 target/riscv: Convert @cs_2 insns to share translation functions
19a398fcf2 target/riscv: Remove decode_RV32_64G()
e5d2d8de1b target/riscv: Remove gen_system()
dd1af1569c target/riscv: Rename trans_arith to gen_arith
927ff74675 target/riscv: Remove manual decoding of RV32/64M insn
822b6f55c2 target/riscv: Remove shift and slt insn manual decoding
482da1143e target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
071d1ed649 target/riscv: Move gen_arith_imm() decoding into trans_* functions
0165b0c416 target/riscv: Remove manual decoding from gen_store()
62fd962e29 target/riscv: Remove manual decoding from gen_load()
0ab2c1ea49 target/riscv: Remove manual decoding from gen_branch()
acd0d70808 target/riscv: Remove gen_jalr()
ad0cbd0254 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
2567da5766 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
60890225d8 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5bd130a674 target/riscv: Convert RV priv insns to decodetree
10d62bd46c target/riscv: Convert RV64D insns to decodetree
65a093bf38 target/riscv: Convert RV32D insns to decodetree
c4f65e1838 target/riscv: Convert RV64F insns to decodetree
6686b81cb9 target/riscv: Convert RV32F insns to decodetree
15ea4f2414 target/riscv: Convert RV64A insns to decodetree
17d3abd7df target/riscv: Convert RV32A insns to decodetree
32e56b1dcf target/riscv: Convert RVXM insns to decodetree
8a5f659685 target/riscv: Convert RVXI csr insns to decodetree
1656880ea1 target/riscv: Convert RVXI fence insns to decodetree
0daef37d04 target/riscv: Convert RVXI arithmetic insns to decodetree
cae0f3ea6a target/riscv: Convert RV64I load/store insns to decodetree
638fd049d7 target/riscv: Convert RV32I load/store insns to decodetree
4e9f599f10 target/riscv: Convert RVXI branch insns to decodetree
9af3b29d8f target/riscv: Activate decodetree and implemnt LUI & AUIPC
=== OUTPUT BEGIN ===
1/34 Checking commit 9af3b29d8f7d (target/riscv: Activate decodetree and
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34:
new file mode 100644
ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1884:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);
total: 1 errors, 1 warnings, 125 lines checked
Patch 1/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
2/34 Checking commit 4e9f599f1041 (target/riscv: Convert RVXI branch insns to
decodetree)
3/34 Checking commit 638fd049d74d (target/riscv: Convert RV32I load/store insns
to decodetree)
4/34 Checking commit cae0f3ea6a4e (target/riscv: Convert RV64I load/store insns
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39:
new file mode 100644
total: 0 errors, 1 warnings, 76 lines checked
Patch 4/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/34 Checking commit 0daef37d049d (target/riscv: Convert RVXI arithmetic insns
to decodetree)
6/34 Checking commit 1656880ea1cd (target/riscv: Convert RVXI fence insns to
decodetree)
7/34 Checking commit 8a5f6596850a (target/riscv: Convert RVXI csr insns to
decodetree)
8/34 Checking commit 32e56b1dcffd (target/riscv: Convert RVXM insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48:
new file mode 100644
total: 0 errors, 1 warnings, 169 lines checked
Patch 8/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/34 Checking commit 17d3abd7df2d (target/riscv: Convert RV32A insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:
new file mode 100644
total: 0 errors, 1 warnings, 199 lines checked
Patch 9/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/34 Checking commit 15ea4f241437 (target/riscv: Convert RV64A insns to
decodetree)
11/34 Checking commit 6686b81cb9ed (target/riscv: Convert RV32F insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#78:
new file mode 100644
total: 0 errors, 1 warnings, 442 lines checked
Patch 11/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/34 Checking commit c4f65e18387e (target/riscv: Convert RV64F insns to
decodetree)
13/34 Checking commit 65a093bf3820 (target/riscv: Convert RV32D insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#51:
new file mode 100644
total: 0 errors, 1 warnings, 398 lines checked
Patch 13/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
14/34 Checking commit 10d62bd46c0b (target/riscv: Convert RV64D insns to
decodetree)
15/34 Checking commit 5bd130a67401 (target/riscv: Convert RV priv insns to
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41:
new file mode 100644
total: 0 errors, 1 warnings, 214 lines checked
Patch 15/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/34 Checking commit 60890225d8b0 (target/riscv: Convert quadrant 0 of RVXC
insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#31:
new file mode 100644
ERROR: externs should be avoided in .c files
#251: FILE: target/riscv/translate.c:1072:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 231 lines checked
Patch 16/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/34 Checking commit 2567da57663f (target/riscv: Convert quadrant 1 of RVXC
insns to decodetree)
18/34 Checking commit ad0cbd02544f (target/riscv: Convert quadrant 2 of RVXC
insns to decodetree)
19/34 Checking commit acd0d70808ce (target/riscv: Remove gen_jalr())
20/34 Checking commit 0ab2c1ea499d (target/riscv: Remove manual decoding from
gen_branch())
21/34 Checking commit 62fd962e29e0 (target/riscv: Remove manual decoding from
gen_load())
22/34 Checking commit 0165b0c41687 (target/riscv: Remove manual decoding from
gen_store())
23/34 Checking commit 071d1ed64975 (target/riscv: Move gen_arith_imm() decoding
into trans_* functions)
24/34 Checking commit 482da1143e3b (target/riscv: make ADD/SUB/OR/XOR/AND insn
use arg lists)
25/34 Checking commit 822b6f55c23d (target/riscv: Remove shift and slt insn
manual decoding)
26/34 Checking commit 927ff7467572 (target/riscv: Remove manual decoding of
RV32/64M insn)
27/34 Checking commit dd1af1569c16 (target/riscv: Rename trans_arith to
gen_arith)
28/34 Checking commit e5d2d8de1bdd (target/riscv: Remove gen_system())
29/34 Checking commit 19a398fcf253 (target/riscv: Remove decode_RV32_64G())
30/34 Checking commit ab13d11898f6 (target/riscv: Convert @cs_2 insns to share
translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#42:
new file mode 100644
ERROR: externs should be avoided in .c files
#182: FILE: target/riscv/translate.c:548:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);
total: 1 errors, 1 warnings, 164 lines checked
Patch 30/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/34 Checking commit e21ef3efe491 (target/riscv: Convert @cl_d, @cl_w, @cs_d,
@cs_w insns)
32/34 Checking commit a79d96ef4f7b (target/riscv: Splice fsw_sd and flw_ld for
riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#28:
new file mode 100644
total: 0 errors, 1 warnings, 309 lines checked
Patch 32/34 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
33/34 Checking commit 69cfc476d22a (target/riscv: Splice remaining compressed
insn pairs for riscv32 vs riscv64)
34/34 Checking commit 6ff2674d6d3e (target/riscv: Remaining rvc insn reuse 32
bit translators)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/address@hidden/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to address@hidden
- [Qemu-devel] [PATCH v8 13/34] target/riscv: Convert RV32D insns to decodetree, (continued)
- [Qemu-devel] [PATCH v8 13/34] target/riscv: Convert RV32D insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 31/34] target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 26/34] target/riscv: Remove manual decoding of RV32/64M insn, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 20/34] target/riscv: Remove manual decoding from gen_branch(), Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 02/34] target/riscv: Convert RVXI branch insns to decodetree, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Bastian Koppelmann, 2019/02/22
- [Qemu-devel] [PATCH v8 32/34] target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64, Bastian Koppelmann, 2019/02/22
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, Alistair Francis, 2019/02/22
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree,
no-reply <=
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27
- Re: [Qemu-devel] [PATCH v8 00/34] target/riscv: Convert to decodetree, no-reply, 2019/02/27