[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 01/38] target/arm: Fill in .opc for cmtst_op
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 01/38] target/arm: Fill in .opc for cmtst_op |
Date: |
Fri, 19 Apr 2019 21:34:05 -1000 |
This allows us to fall back to integers if the tcg backend
does not support comparisons in the given vece.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d408e4d7ef..13e2dc6562 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6140,16 +6140,20 @@ static void gen_cmtst_vec(unsigned vece, TCGv_vec d,
TCGv_vec a, TCGv_vec b)
const GVecGen3 cmtst_op[4] = {
{ .fni4 = gen_helper_neon_tst_u8,
.fniv = gen_cmtst_vec,
+ .opc = INDEX_op_cmp_vec,
.vece = MO_8 },
{ .fni4 = gen_helper_neon_tst_u16,
.fniv = gen_cmtst_vec,
+ .opc = INDEX_op_cmp_vec,
.vece = MO_16 },
{ .fni4 = gen_cmtst_i32,
.fniv = gen_cmtst_vec,
+ .opc = INDEX_op_cmp_vec,
.vece = MO_32 },
{ .fni8 = gen_cmtst_i64,
.fniv = gen_cmtst_vec,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
+ .opc = INDEX_op_cmp_vec,
.vece = MO_64 },
};
--
2.17.1
- [Qemu-devel] [PATCH 00/38] tcg vector improvements, Richard Henderson, 2019/04/20
- [Qemu-devel] [PATCH 01/38] target/arm: Fill in .opc for cmtst_op,
Richard Henderson <=
- [Qemu-devel] [PATCH 02/38] tcg: Assert fixed_reg is read-only, Richard Henderson, 2019/04/20
- [Qemu-devel] [PATCH 04/38] tcg: Support cross-class moves without instruction support, Richard Henderson, 2019/04/20
- [Qemu-devel] [PATCH 03/38] tcg: Return bool success from tcg_out_mov, Richard Henderson, 2019/04/20
- [Qemu-devel] [PATCH 05/38] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded, Richard Henderson, 2019/04/20