Re: [Qemu-devel] [PATCH v3 29/39] target/unicore32: Use env_cpu, env_archcpu

[Alistair Francis]

On Tue, May 7, 2019 at 5:30 PM Richard Henderson
<address@hidden> wrote:
>
> Reviewed-by: Peter Maydell <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>

Reviewed-by: Alistair Francis <address@hidden>

Alistair

> ---
>  target/unicore32/cpu.h          |  5 -----
>  hw/unicore32/puv3.c             |  2 +-
>  target/unicore32/helper.c       |  8 ++------
>  target/unicore32/op_helper.c    |  2 +-
>  target/unicore32/softmmu.c      | 11 ++++-------
>  target/unicore32/translate.c    | 26 ++------------------------
>  target/unicore32/ucf64_helper.c |  2 +-
>  7 files changed, 11 insertions(+), 45 deletions(-)
>
> diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
> index 22e22345dc..2dd1b34765 100644
> --- a/target/unicore32/cpu.h
> +++ b/target/unicore32/cpu.h
> @@ -76,11 +76,6 @@ struct UniCore32CPU {
>      CPUUniCore32State env;
>  };
>
> -static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env)
> -{
> -    return container_of(env, UniCore32CPU, env);
> -}
> -
>  #define ENV_OFFSET offsetof(UniCore32CPU, env)
>
>  void uc32_cpu_do_interrupt(CPUState *cpu);
> diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c
> index b42e600f74..132e6086ee 100644
> --- a/hw/unicore32/puv3.c
> +++ b/hw/unicore32/puv3.c
> @@ -56,7 +56,7 @@ static void puv3_soc_init(CPUUniCore32State *env)
>
>      /* Initialize interrupt controller */
>      cpu_intc = qemu_allocate_irq(puv3_intc_cpu_handler,
> -                                 uc32_env_get_cpu(env), 0);
> +                                 env_archcpu(env), 0);
>      dev = sysbus_create_simple("puv3_intc", PUV3_INTC_BASE, cpu_intc);
>      for (i = 0; i < PUV3_IRQS_NR; i++) {
>          irqs[i] = qdev_get_gpio_in(dev, i);
> diff --git a/target/unicore32/helper.c b/target/unicore32/helper.c
> index a5ff2ddb74..19ba865482 100644
> --- a/target/unicore32/helper.c
> +++ b/target/unicore32/helper.c
> @@ -31,8 +31,6 @@
>  void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
>          uint32_t cop)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      /*
>       * movc pp.nn, rn, #imm9
>       *      rn: UCOP_REG_D
> @@ -101,7 +99,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, 
> uint32_t creg,
>      case 6:
>          if ((cop <= 6) && (cop >= 2)) {
>              /* invalid all tlb */
> -            tlb_flush(CPU(cpu));
> +            tlb_flush(env_cpu(env));
>              return;
>          }
>          break;
> @@ -218,10 +216,8 @@ void helper_cp1_putc(target_ulong x)
>  #ifdef CONFIG_USER_ONLY
>  void switch_mode(CPUUniCore32State *env, int mode)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      if (mode != ASR_MODE_USER) {
> -        cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> +        cpu_abort(env_cpu(env), "Tried to switch out of user mode\n");
>      }
>  }
>
> diff --git a/target/unicore32/op_helper.c b/target/unicore32/op_helper.c
> index e0a15882d3..44ff84420e 100644
> --- a/target/unicore32/op_helper.c
> +++ b/target/unicore32/op_helper.c
> @@ -19,7 +19,7 @@
>
>  void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
>  {
> -    CPUState *cs = CPU(uc32_env_get_cpu(env));
> +    CPUState *cs = env_cpu(env);
>
>      cs->exception_index = excp;
>      cpu_loop_exit(cs);
> diff --git a/target/unicore32/softmmu.c b/target/unicore32/softmmu.c
> index 00c7e0d028..2f31592faf 100644
> --- a/target/unicore32/softmmu.c
> +++ b/target/unicore32/softmmu.c
> @@ -36,8 +36,6 @@
>  /* Map CPU modes onto saved register banks.  */
>  static inline int bank_number(CPUUniCore32State *env, int mode)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      switch (mode) {
>      case ASR_MODE_USER:
>      case ASR_MODE_SUSR:
> @@ -51,7 +49,7 @@ static inline int bank_number(CPUUniCore32State *env, int 
> mode)
>      case ASR_MODE_INTR:
>          return 4;
>      }
> -    cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
> +    cpu_abort(env_cpu(env), "Bad mode %x\n", mode);
>      return -1;
>  }
>
> @@ -126,8 +124,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, 
> uint32_t address,
>          int access_type, int is_user, uint32_t *phys_ptr, int *prot,
>          target_ulong *page_size)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -    CPUState *cs = CPU(cpu);
> +    CPUState *cs = env_cpu(env);
>      int code;
>      uint32_t table;
>      uint32_t desc;
> @@ -174,11 +171,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, 
> uint32_t address,
>              *page_size = TARGET_PAGE_SIZE;
>              break;
>          default:
> -            cpu_abort(CPU(cpu), "wrong page type!");
> +            cpu_abort(cs, "wrong page type!");
>          }
>          break;
>      default:
> -        cpu_abort(CPU(cpu), "wrong page type!");
> +        cpu_abort(cs, "wrong page type!");
>      }
>
>      *phys_ptr = phys_addr;
> diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
> index 89b02d1c3c..d27451eed3 100644
> --- a/target/unicore32/translate.c
> +++ b/target/unicore32/translate.c
> @@ -180,7 +180,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
>  #define UCOP_SET_L              UCOP_SET(24)
>  #define UCOP_SET_S              UCOP_SET(24)
>
> -#define ILLEGAL         cpu_abort(CPU(cpu),                             \
> +#define ILLEGAL         cpu_abort(env_cpu(env),                         \
>                          "Illegal UniCore32 instruction %x at line %d!", \
>                          insn, __LINE__)
>
> @@ -188,7 +188,6 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
>  static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
>          uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      TCGv tmp, tmp2, tmp3;
>      if ((insn & 0xfe000000) == 0xe0000000) {
>          tmp2 = new_tmp();
> @@ -214,7 +213,6 @@ static void disas_cp0_insn(CPUUniCore32State *env, 
> DisasContext *s,
>  static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
>          uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      TCGv tmp;
>
>      if ((insn & 0xff003fff) == 0xe1000400) {
> @@ -682,7 +680,6 @@ static inline long ucf64_reg_offset(int reg)
>  /* UniCore-F64 single load/store I_offset */
>  static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, 
> uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      int offset;
>      TCGv tmp;
>      TCGv addr;
> @@ -729,7 +726,6 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, 
> DisasContext *s, uint32_t in
>  /* UniCore-F64 load/store multiple words */
>  static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, 
> uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      unsigned int i;
>      int j, n, freg;
>      TCGv tmp;
> @@ -815,7 +811,6 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, 
> DisasContext *s, uint32_t in
>  /* UniCore-F64 mrc/mcr */
>  static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t 
> insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      TCGv tmp;
>
>      if ((insn & 0xfe0003ff) == 0xe2000000) {
> @@ -880,8 +875,6 @@ static void do_ucf64_trans(CPUUniCore32State *env, 
> DisasContext *s, uint32_t ins
>  /* UniCore-F64 convert instructions */
>  static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t 
> insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      if (UCOP_UCF64_FMT == 3) {
>          ILLEGAL;
>      }
> @@ -948,8 +941,6 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn
>  /* UniCore-F64 compare instructions */
>  static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t 
> insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      if (UCOP_SET(25)) {
>          ILLEGAL;
>      }
> @@ -1028,8 +1019,6 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn
>  /* UniCore-F64 data processing */
>  static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t 
> insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      if (UCOP_UCF64_FMT == 3) {
>          ILLEGAL;
>      }
> @@ -1063,8 +1052,6 @@ static void do_ucf64_datap(CPUUniCore32State *env, 
> DisasContext *s, uint32_t ins
>  /* Disassemble an F64 instruction */
>  static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, 
> uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      if (!UCOP_SET(29)) {
>          if (UCOP_SET(26)) {
>              do_ucf64_ldst_m(env, s, insn);
> @@ -1162,8 +1149,6 @@ static void gen_exception_return(DisasContext *s, TCGv 
> pc)
>  static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
>          uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> -
>      switch (UCOP_CPNUM) {
>  #ifndef CONFIG_USER_ONLY
>      case 0:
> @@ -1178,14 +1163,13 @@ static void disas_coproc_insn(CPUUniCore32State *env, 
> DisasContext *s,
>          break;
>      default:
>          /* Unknown coprocessor. */
> -        cpu_abort(CPU(cpu), "Unknown coprocessor!");
> +        cpu_abort(env_cpu(env), "Unknown coprocessor!");
>      }
>  }
>
>  /* data processing instructions */
>  static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      TCGv tmp;
>      TCGv tmp2;
>      int logic_cc;
> @@ -1419,7 +1403,6 @@ static void do_mult(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn)
>  /* miscellaneous instructions */
>  static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      unsigned int val;
>      TCGv tmp;
>
> @@ -1545,7 +1528,6 @@ static void do_ldst_ir(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn)
>  /* SWP instruction */
>  static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      TCGv addr;
>      TCGv tmp;
>      TCGv tmp2;
> @@ -1573,7 +1555,6 @@ static void do_swap(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn)
>  /* load/store hw/sb */
>  static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t 
> insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      TCGv addr;
>      TCGv tmp;
>
> @@ -1626,7 +1607,6 @@ static void do_ldst_hwsb(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn)
>  /* load/store multiple words */
>  static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      unsigned int val, i, mmu_idx;
>      int j, n, reg, user, loaded_base;
>      TCGv tmp;
> @@ -1768,7 +1748,6 @@ static void do_ldst_m(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn)
>  /* branch (and link) */
>  static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      unsigned int val;
>      int32_t offset;
>      TCGv tmp;
> @@ -1798,7 +1777,6 @@ static void do_branch(CPUUniCore32State *env, 
> DisasContext *s, uint32_t insn)
>
>  static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
>      unsigned int insn;
>
>      insn = cpu_ldl_code(env, s->pc);
> diff --git a/target/unicore32/ucf64_helper.c b/target/unicore32/ucf64_helper.c
> index fad3fa6618..e078e84437 100644
> --- a/target/unicore32/ucf64_helper.c
> +++ b/target/unicore32/ucf64_helper.c
> @@ -78,7 +78,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
>
>  void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
>  {
> -    UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +    UniCore32CPU *cpu = env_archcpu(env);
>      int i;
>      uint32_t changed;
>
> --
> 2.17.1
>
>