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[Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of t
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h |
Date: |
Tue, 10 Sep 2019 12:04:46 -0700 |
From: Bin Meng <address@hidden>
The inclusion of "target/riscv/cpu.h" is unnecessary in various
sifive model drivers.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_prci.c | 1 -
hw/riscv/sifive_test.c | 1 -
hw/riscv/sifive_uart.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 982fbb26fd..c413f0cb76 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -22,7 +22,6 @@
#include "hw/sysbus.h"
#include "qemu/log.h"
#include "qemu/module.h"
-#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_prci.h"
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index aa544e7428..339195c6ff 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -23,7 +23,6 @@
#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
-#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/riscv/sifive_test.h"
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 215990b443..a403ae90f5 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -22,7 +22,6 @@
#include "hw/sysbus.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
-#include "target/riscv/cpu.h"
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/riscv/sifive_uart.h"
--
2.21.0
- [Qemu-devel] [PULL 13/47] riscv: sifive_test: Add reset functionality, (continued)
- [Qemu-devel] [PULL 13/47] riscv: sifive_test: Add reset functionality, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 12/47] riscv: hmp: Add a command to show virtual memory mappings, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 18/47] riscv: hw: Change create_fdt() to return void, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/11