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[Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology con
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string |
Date: |
Tue, 10 Sep 2019 12:04:58 -0700 |
From: Bin Meng <address@hidden>
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau <address@hidden>
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 6c4634dcac..713c451e85 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -424,10 +424,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev,
Error **errp)
plic_hart_config = g_malloc0(plic_hart_config_len);
for (i = 0; i < ms->smp.cpus; i++) {
if (i != 0) {
- strncat(plic_hart_config, ",", plic_hart_config_len);
+ strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
+ plic_hart_config_len);
+ } else {
+ strncat(plic_hart_config, "M", plic_hart_config_len);
}
- strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
- plic_hart_config_len);
plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
}
--
2.21.0
- [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images, (continued)
- [Qemu-devel] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/11
- [Qemu-devel] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/11