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[Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floa
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point |
Date: |
Wed, 18 Sep 2019 07:56:39 -0700 |
From: Alistair Francis <address@hidden>
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb
flags.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 16efe8c860..124ed33ee4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -301,7 +301,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env,
target_ulong *pc,
#else
*flags = cpu_mmu_index(env, 0);
if (riscv_cpu_fp_enabled(env)) {
- *flags |= env->mstatus & MSTATUS_FS;
+ *flags |= TB_FLAGS_MSTATUS_FS;
}
#endif
}
--
2.21.0
- [Qemu-devel] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC, (continued)
- [Qemu-devel] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 46/48] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 10/48] riscv: Add a helper routine for finding firmware, Palmer Dabbelt, 2019/09/18
- Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3, Peter Maydell, 2019/09/19