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[Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers |
Date: |
Wed, 18 Sep 2019 07:56:40 -0700 |
From: KONRAD Frederic <address@hidden>
While debugging an application with GDB the following might happen:
(gdb) return
Make xxx return now? (y or n) y
Could not fetch register "fflags"; remote failure reply 'E14'
This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
number (8). It should use the csr_register_map in order to reach the
riscv_cpu_get_fflags callback.
Signed-off-by: KONRAD Frederic <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/gdbstub.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 27be93279b..ded140e8d8 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t
*mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
+ 0, 0);
if (result == 0) {
return gdb_get_regl(mem_buf, val);
}
@@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t
*mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
+ val, -1);
if (result == 0) {
return sizeof(target_ulong);
}
--
2.21.0
- [Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, (continued)
- [Qemu-devel] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 46/48] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Palmer Dabbelt, 2019/09/18
- [Qemu-devel] [PULL 48/48] gdbstub: riscv: fix the fflags registers,
Palmer Dabbelt <=
- [Qemu-devel] [PULL 10/48] riscv: Add a helper routine for finding firmware, Palmer Dabbelt, 2019/09/18
- Re: [Qemu-devel] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3, Peter Maydell, 2019/09/19