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[PULL 46/68] aspeed/timer: Add support for IRQ status register on the AS
From: |
Peter Maydell |
Subject: |
[PULL 46/68] aspeed/timer: Add support for IRQ status register on the AST2600 |
Date: |
Mon, 14 Oct 2019 17:03:42 +0100 |
From: Cédric Le Goater <address@hidden>
The AST2600 timer replaces control register 2 with a interrupt status
register. It is set by hardware when an IRQ occurs and cleared by
software.
Modify the vmstate version to take into account the new fields.
Based on previous work from Joel Stanley.
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/timer/aspeed_timer.h | 1 +
hw/timer/aspeed_timer.c | 36 +++++++++++++++++++++++++--------
2 files changed, 29 insertions(+), 8 deletions(-)
diff --git a/include/hw/timer/aspeed_timer.h b/include/hw/timer/aspeed_timer.h
index 69b1377af01..948329893c0 100644
--- a/include/hw/timer/aspeed_timer.h
+++ b/include/hw/timer/aspeed_timer.h
@@ -60,6 +60,7 @@ typedef struct AspeedTimerCtrlState {
uint32_t ctrl;
uint32_t ctrl2;
uint32_t ctrl3;
+ uint32_t irq_sts;
AspeedTimer timers[ASPEED_TIMER_NR_TIMERS];
AspeedSCUState *scu;
diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c
index 7f73d0c7533..bcce2192a92 100644
--- a/hw/timer/aspeed_timer.c
+++ b/hw/timer/aspeed_timer.c
@@ -160,7 +160,9 @@ static uint64_t calculate_next(struct AspeedTimer *t)
timer_del(&t->timer);
if (timer_overflow_interrupt(t)) {
+ AspeedTimerCtrlState *s = timer_to_ctrl(t);
t->level = !t->level;
+ s->irq_sts |= BIT(t->id);
qemu_set_irq(t->irq, t->level);
}
@@ -199,7 +201,9 @@ static void aspeed_timer_expire(void *opaque)
}
if (interrupt) {
+ AspeedTimerCtrlState *s = timer_to_ctrl(t);
t->level = !t->level;
+ s->irq_sts |= BIT(t->id);
qemu_set_irq(t->irq, t->level);
}
@@ -244,9 +248,6 @@ static uint64_t aspeed_timer_read(void *opaque, hwaddr
offset, unsigned size)
case 0x30: /* Control Register */
value = s->ctrl;
break;
- case 0x34: /* Control Register 2 */
- value = s->ctrl2;
- break;
case 0x00 ... 0x2c: /* Timers 1 - 4 */
value = aspeed_timer_get_value(&s->timers[(offset >> 4)], reg);
break;
@@ -438,9 +439,6 @@ static void aspeed_timer_write(void *opaque, hwaddr offset,
uint64_t value,
case 0x30:
aspeed_timer_set_ctrl(s, tv);
break;
- case 0x34:
- aspeed_timer_set_ctrl2(s, tv);
- break;
/* Timer Registers */
case 0x00 ... 0x2c:
aspeed_timer_set_value(s, (offset >> TIMER_NR_REGS), reg, tv);
@@ -468,6 +466,9 @@ static uint64_t aspeed_2400_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
uint64_t value;
switch (offset) {
+ case 0x34:
+ value = s->ctrl2;
+ break;
case 0x38:
case 0x3C:
default:
@@ -482,7 +483,12 @@ static uint64_t
aspeed_2400_timer_read(AspeedTimerCtrlState *s, hwaddr offset)
static void aspeed_2400_timer_write(AspeedTimerCtrlState *s, hwaddr offset,
uint64_t value)
{
+ const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
+
switch (offset) {
+ case 0x34:
+ aspeed_timer_set_ctrl2(s, tv);
+ break;
case 0x38:
case 0x3C:
default:
@@ -497,6 +503,9 @@ static uint64_t aspeed_2500_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
uint64_t value;
switch (offset) {
+ case 0x34:
+ value = s->ctrl2;
+ break;
case 0x38:
value = s->ctrl3 & BIT(0);
break;
@@ -517,6 +526,9 @@ static void aspeed_2500_timer_write(AspeedTimerCtrlState
*s, hwaddr offset,
uint8_t command;
switch (offset) {
+ case 0x34:
+ aspeed_timer_set_ctrl2(s, tv);
+ break;
case 0x38:
command = (value >> 1) & 0xFF;
if (command == 0xAE) {
@@ -543,6 +555,9 @@ static uint64_t aspeed_2600_timer_read(AspeedTimerCtrlState
*s, hwaddr offset)
uint64_t value;
switch (offset) {
+ case 0x34:
+ value = s->irq_sts;
+ break;
case 0x38:
case 0x3C:
default:
@@ -560,6 +575,9 @@ static void aspeed_2600_timer_write(AspeedTimerCtrlState
*s, hwaddr offset,
const uint32_t tv = (uint32_t)(value & 0xFFFFFFFF);
switch (offset) {
+ case 0x34:
+ s->irq_sts &= tv;
+ break;
case 0x3C:
aspeed_timer_set_ctrl(s, s->ctrl & ~tv);
break;
@@ -626,6 +644,7 @@ static void aspeed_timer_reset(DeviceState *dev)
s->ctrl = 0;
s->ctrl2 = 0;
s->ctrl3 = 0;
+ s->irq_sts = 0;
}
static const VMStateDescription vmstate_aspeed_timer = {
@@ -644,12 +663,13 @@ static const VMStateDescription vmstate_aspeed_timer = {
static const VMStateDescription vmstate_aspeed_timer_state = {
.name = "aspeed.timerctrl",
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctrl, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl2, AspeedTimerCtrlState),
VMSTATE_UINT32(ctrl3, AspeedTimerCtrlState),
+ VMSTATE_UINT32(irq_sts, AspeedTimerCtrlState),
VMSTATE_STRUCT_ARRAY(timers, AspeedTimerCtrlState,
ASPEED_TIMER_NR_TIMERS, 1, vmstate_aspeed_timer,
AspeedTimer),
--
2.20.1
- [PULL 36/68] target/arm/arm-semi: Factor out implementation of SYS_FLEN, (continued)
- [PULL 36/68] target/arm/arm-semi: Factor out implementation of SYS_FLEN, Peter Maydell, 2019/10/14
- [PULL 37/68] target/arm/arm-semi: Implement support for semihosting feature detection, Peter Maydell, 2019/10/14
- [PULL 38/68] target/arm/arm-semi: Implement SH_EXT_EXIT_EXTENDED extension, Peter Maydell, 2019/10/14
- [PULL 39/68] target/arm/arm-semi: Implement SH_EXT_STDOUT_STDERR extension, Peter Maydell, 2019/10/14
- [PULL 40/68] aspeed/wdt: Check correct register for clock source, Peter Maydell, 2019/10/14
- [PULL 41/68] hw/sd/aspeed_sdhci: New device, Peter Maydell, 2019/10/14
- [PULL 44/68] aspeed/timer: Add support for control register 3, Peter Maydell, 2019/10/14
- [PULL 42/68] hw: aspeed_scu: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 43/68] aspeed/timer: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 45/68] aspeed/timer: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 46/68] aspeed/timer: Add support for IRQ status register on the AST2600,
Peter Maydell <=
- [PULL 47/68] aspeed/sdmc: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 48/68] aspeed/sdmc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 50/68] hw: wdt_aspeed: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 49/68] watchdog/aspeed: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 52/68] aspeed/smc: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 51/68] aspeed/smc: Introduce segment operations, Peter Maydell, 2019/10/14
- [PULL 53/68] hw/gpio: Add in AST2600 specific implementation, Peter Maydell, 2019/10/14
- [PULL 55/68] aspeed/i2c: Add AST2600 support, Peter Maydell, 2019/10/14
- [PULL 54/68] aspeed/i2c: Introduce an object class per SoC, Peter Maydell, 2019/10/14
- [PULL 58/68] m25p80: Add support for w25q512jv, Peter Maydell, 2019/10/14