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Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2
From: |
Peter Maydell |
Subject: |
Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 |
Date: |
Tue, 29 Oct 2019 08:37:53 +0000 |
On Mon, 28 Oct 2019 at 15:58, Palmer Dabbelt <address@hidden> wrote:
>
> merged tag 'for_upstream'
> Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
> Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
> The following changes since commit 9bb73502321d46f4d320fa17aa38201445783fc4:
>
> Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging
> (2019-10-28 13:32:40 +0000)
>
> are available in the Git repository at:
>
> git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.2-sf2
>
> for you to fetch changes up to 9667e53573f907d4fcd6accff1c8fe525544b749:
>
> target/riscv: PMP violation due to wrong size parameter (2019-10-28
> 08:46:33 -0700)
>
> ----------------------------------------------------------------
> RISC-V Patches for the 4.2 Soft Freeze, Part 2
>
> This patch set contains a handful of small fixes for RISC-V targets that
> I'd like to target for the 4.2 soft freeze. They include:
>
> * A fix to allow the debugger to access the state of all privilege
> modes, as opposed to just the currently executing one.
> * A pair of cleanups to implement cpu_do_transaction_failed.
> * Fixes to the device tree.
> * The addition of various memory regions to make the sifive_u machine
> more closely match the HiFive Unleashed board.
> * Fixes to our GDB interface to allow CSRs to be accessed.
> * A fix to a memory leak pointed out by coverity.
> * A fix that prevents PMP checks from firing incorrectly.
>
> This passes "make chcek" and boots Open Embedded for me.
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.
-- PMM
- [PULL 09/18] riscv/sifive_u: Manually define the machine, (continued)
- [PULL 09/18] riscv/sifive_u: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 10/18] riscv/sifive_u: Add the start-in-flash property, Palmer Dabbelt, 2019/10/28
- [PULL 11/18] riscv/virt: Manually define the machine, Palmer Dabbelt, 2019/10/28
- [PULL 12/18] riscv/virt: Add the PFlash CFI01 device, Palmer Dabbelt, 2019/10/28
- [PULL 13/18] riscv/virt: Jump to pflash if specified, Palmer Dabbelt, 2019/10/28
- [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs, Palmer Dabbelt, 2019/10/28
- [PULL 16/18] target/riscv: Make the priv register writable by GDB, Palmer Dabbelt, 2019/10/28
- [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads, Palmer Dabbelt, 2019/10/28
- [PULL 17/18] riscv/boot: Fix possible memory leak, Palmer Dabbelt, 2019/10/28
- [PULL 18/18] target/riscv: PMP violation due to wrong size parameter, Palmer Dabbelt, 2019/10/28
- Re: [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2,
Peter Maydell <=