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Re: [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model


From: Eduardo Habkost
Subject: Re: [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model
Date: Tue, 5 Nov 2019 18:43:25 -0300

On Tue, Nov 05, 2019 at 09:17:30PM +0000, Moger, Babu wrote:
> Adds the following missing CPUID bits:
> perfctr-core : core performance counter extensions support. Enables the VM
>                to use extended performance counter support. It enables six
>                programmable counters instead of 4 counters.
> clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
> xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
>                pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
>                pointers.
> ibpb         : Indirect Branch Prediction Barrie.
> xsaves       : XSAVES, XRSTORS and IA32_XSS supported.
> 
> Depends on:
> 40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
> 504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
> 52297436199d ("kvm: svm: Update svm_xsaves_supported")
> 
> Signed-off-by: Babu Moger <address@hidden>
> ---
>  hw/i386/pc.c      |    8 +++++++-
>  target/i386/cpu.c |   11 +++++------
>  2 files changed, 12 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 51b72439b4..a72fe1db31 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -105,7 +105,13 @@ struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
>  /* Physical Address of PVH entry point read from kernel ELF NOTE */
>  static size_t pvh_start_addr;
>  
> -GlobalProperty pc_compat_4_1[] = {};
> +GlobalProperty pc_compat_4_1[] = {
> +    { "EPYC" "-" TYPE_X86_CPU, "perfctr-core", "off" },
> +    { "EPYC" "-" TYPE_X86_CPU, "clzero", "off" },
> +    { "EPYC" "-" TYPE_X86_CPU, "xsaveerptr", "off" },
> +    { "EPYC" "-" TYPE_X86_CPU, "ibpb", "off" },
> +    { "EPYC" "-" TYPE_X86_CPU, "xsaves", "off" },
> +};

machine-type-based CPU compatibility was now replaced by
versioned CPU models.  Please use the X86CPUDefinition.versions
field to add a new version of EPYC instead.

>  const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
>  
>  GlobalProperty pc_compat_4_0[] = {};
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 07cf562d89..71233e6310 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3110,19 +3110,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
>              CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
>              CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
>              CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
> -            CPUID_EXT3_TOPOEXT,
> +            CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
> +        .features[FEAT_8000_0008_EBX] =
> +            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
> +            CPUID_8000_0008_EBX_IBPB,
>          .features[FEAT_7_0_EBX] =
>              CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 
> |
>              CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
>              CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | 
> CPUID_7_0_EBX_CLFLUSHOPT |
>              CPUID_7_0_EBX_SHA_NI,
> -        /* Missing: XSAVES (not supported by some Linux versions,
> -         * including v4.1 to v4.12).
> -         * KVM doesn't yet expose any XSAVES state save component.
> -         */
>          .features[FEAT_XSAVE] =
>              CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> -            CPUID_XSAVE_XGETBV1,
> +            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
>          .features[FEAT_6_EAX] =
>              CPUID_6_EAX_ARAT,
>          .features[FEAT_SVM] =
> 

-- 
Eduardo




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