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[PATCH v5 20/41] target/arm: Add regime_has_2_ranges
From: |
Richard Henderson |
Subject: |
[PATCH v5 20/41] target/arm: Add regime_has_2_ranges |
Date: |
Wed, 29 Jan 2020 15:55:53 -0800 |
Create a predicate to indicate whether the regime has
both positive and negative addresses.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/internals.h | 18 ++++++++++++++++++
target/arm/helper.c | 23 ++++++-----------------
target/arm/translate-a64.c | 3 +--
3 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 0c4119a3a2..6d4a942bde 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -837,6 +837,24 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu)
}
}
+/* Return true if this address translation regime has two ranges. */
+static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
+{
+ switch (mmu_idx) {
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ case ARMMMUIdx_SE10_0:
+ case ARMMMUIdx_SE10_1:
+ return true;
+ default:
+ return false;
+ }
+}
+
/* Return true if this address translation regime is secure */
static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
{
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bf9d85e484..aba79db2a1 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -9030,15 +9030,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx
mmu_idx, bool is_aa64,
}
if (is_aa64) {
- switch (regime_el(env, mmu_idx)) {
- case 1:
- if (!is_user) {
- xn = pxn || (user_rw & PAGE_WRITE);
- }
- break;
- case 2:
- case 3:
- break;
+ if (regime_has_2_ranges(mmu_idx) && !is_user) {
+ xn = pxn || (user_rw & PAGE_WRITE);
}
} else if (arm_feature(env, ARM_FEATURE_V7)) {
switch (regime_el(env, mmu_idx)) {
@@ -9572,7 +9565,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env,
uint64_t va,
ARMMMUIdx mmu_idx)
{
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
- uint32_t el = regime_el(env, mmu_idx);
bool tbi, tbid, epd, hpd, using16k, using64k;
int select, tsz;
@@ -9582,7 +9574,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env,
uint64_t va,
*/
select = extract64(va, 55, 1);
- if (el > 1) {
+ if (!regime_has_2_ranges(mmu_idx)) {
tsz = extract32(tcr, 0, 6);
using64k = extract32(tcr, 14, 1);
using16k = extract32(tcr, 15, 1);
@@ -9738,10 +9730,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
param = aa64_va_parameters(env, address, mmu_idx,
access_type != MMU_INST_FETCH);
level = 0;
- /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
- * invalid.
- */
- ttbr1_valid = (el < 2);
+ ttbr1_valid = regime_has_2_ranges(mmu_idx);
addrsize = 64 - 8 * param.tbi;
inputsize = 64 - param.tsz;
} else {
@@ -11457,8 +11446,8 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env,
int el, int fp_el,
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
- if (regime_el(env, stage1) < 2) {
+ /* Get control bits for tagged addresses. */
+ if (regime_has_2_ranges(mmu_idx)) {
ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
tbid = (p1.tbi << 1) | p0.tbi;
tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 4ec6f0dad1..9cac6c9232 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -175,8 +175,7 @@ static void gen_top_byte_ignore(DisasContext *s, TCGv_i64
dst,
if (tbi == 0) {
/* Load unmodified address */
tcg_gen_mov_i64(dst, src);
- } else if (s->current_el >= 2) {
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
+ } else if (!regime_has_2_ranges(s->mmu_idx)) {
/* Force tag byte to all zero */
tcg_gen_extract_i64(dst, src, 0, 56);
} else {
--
2.20.1
- [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, (continued)
- [PATCH v5 11/41] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2020/01/29
- [PATCH v5 14/41] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2020/01/29
- [PATCH v5 12/41] target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01], Richard Henderson, 2020/01/29
- [PATCH v5 13/41] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2020/01/29
- [PATCH v5 16/41] target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits, Richard Henderson, 2020/01/29
- [PATCH v5 15/41] target/arm: Recover 4 bits from TBFLAGs, Richard Henderson, 2020/01/29
- [PATCH v5 17/41] target/arm: Rearrange ARMMMUIdxBit, Richard Henderson, 2020/01/29
- [PATCH v5 10/41] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2020/01/29
- [PATCH v5 18/41] target/arm: Tidy ARMMMUIdx m-profile definitions, Richard Henderson, 2020/01/29
- [PATCH v5 19/41] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2020/01/29
- [PATCH v5 20/41] target/arm: Add regime_has_2_ranges,
Richard Henderson <=
- [PATCH v5 23/41] target/arm: Update aa64_zva_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 21/41] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 22/41] target/arm: Update arm_sctlr for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 25/41] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2020/01/29
- [PATCH v5 24/41] target/arm: Update ctr_el0_access for EL2, Richard Henderson, 2020/01/29
- [PATCH v5 27/41] target/arm: Update define_one_arm_cp_reg_with_opaque for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 26/41] target/arm: Update timer access for VHE, Richard Henderson, 2020/01/29
- [PATCH v5 30/41] target/arm: Flush tlb for ASID changes in EL2&0 translation regime, Richard Henderson, 2020/01/29