Re: [PATCH] hw/ide: Remove status register read side effect

[jasper.lowell]

> Yes, that's correct. However I'm quite confident from booting other
> non-Solaris OSs
> under qemu-system-sparc64 that PCI native mode is being used,
> particularly as it is
> possible to see the related PCI sabre IRQ routing configuration
> changes.

Considering that Solaris 10 is accessing CFR and ARTTIM23 I don't think
there is any doubt that it is using the chip in PCI native mode. I
don't think Solaris 10 even has support for legacy mode.

Thanks,
Jasper Lowell.

On Wed, 2020-03-04 at 21:07 +0000, Mark Cave-Ayland wrote:
> On 04/03/2020 03:11, address@hidden wrote:
> 
> > > cmd646_update_irq() only seems to raise PCI interrupt, should it
> > > also
> > > have 
> > > an option to use INT 14 and 15 in legacy mode similar to what my
> > > patch 
> > > does for via-ide?
> > 
> > Looking through /qemu/hw/ide/cmd646.c it doesn't look like QEMU has
> > support for legacy mode. At the very least, it looks like we
> > default to
> > PCI native mode:
> > 
> > static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp)
> >     ...
> >     pci_conf[PCI_CLASS_PROG] = 0x8f;
> >     ...
> > 
> > To add support for legacy mode it would require changing
> > cmd646_update_irq() and maybe cmd646_set_irq() so that interrupts
> > are
> > conditionally raised on IRQ14 and/or IRQ15 when the ports are in
> > legacy
> > mode.
> 
> Yes, that's correct. However I'm quite confident from booting other
> non-Solaris OSs
> under qemu-system-sparc64 that PCI native mode is being used,
> particularly as it is
> possible to see the related PCI sabre IRQ routing configuration
> changes.
> 
> 
> ATB,
> 
> Mark.