Re: [PATCH v6 11/13] target/i386: Enable new apic id encoding for EPYC based cpus models

[Igor Mammedov]

On Tue, 10 Mar 2020 21:34:32 -0500
Babu Moger <address@hidden> wrote:

> The APIC ID is decoded based on the sequence sockets->dies->cores->threads.
> This works fine for most standard AMD and other vendors' configurations,
> but this decoding sequence does not follow that of AMD's APIC ID enumeration
> strictly. In some cases this can cause CPU topology inconsistency.
> 
> When booting a guest VM, the kernel tries to validate the topology, and finds
> it inconsistent with the enumeration of EPYC cpu models. The more details are
> in the bug https://bugzilla.redhat.com/show_bug.cgi?id=1728166.
> 
> To fix the problem we need to build the topology as per the Processor
> Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
> Processors. The documentation is available from the bugzilla Link below.
> 
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
> It is also available at
> https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip
> 
> Here is the text from the PPR.
> Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize], 
> the
> number of least significant bits in the Initial APIC ID that indicate core ID
> within a processor, in constructing per-core CPUID masks.
> Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores
> (MNC) that the processor could theoretically support, not the actual number of
> cores that are actually implemented or enabled on the processor, as indicated
> by Core::X86::Cpuid::SizeId[NC].
> Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
> • ApicId[6] = Socket ID.
> • ApicId[5:4] = Node ID.
> • ApicId[3] = Logical CCX L3 complex ID
> • ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} : 
> {1'b0,LogicalCoreID[1:0]}
> 
> The new apic id encoding is enabled for EPYC and EPYC-Rome models.
> 
> Signed-off-by: Babu Moger <address@hidden>
> Acked-by: Michael S. Tsirkin <address@hidden>

Acked-by: Igor Mammedov <address@hidden>

> ---
>  target/i386/cpu.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 19de79d01c..5d5734af76 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3921,6 +3921,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .xlevel = 0x8000001E,
>          .model_id = "AMD EPYC Processor",
>          .cache_info = &epyc_cache_info,
> +        .use_epyc_apic_id_encoding = 1,
>          .versions = (X86CPUVersionDefinition[]) {
>              { .version = 1 },
>              {
> @@ -4048,6 +4049,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .xlevel = 0x8000001E,
>          .model_id = "AMD EPYC-Rome Processor",
>          .cache_info = &epyc_rome_cache_info,
> +        .use_epyc_apic_id_encoding = 1,
>      },
>  };
>  
>