[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply
|
From: |
Richard Henderson |
|
Subject: |
Re: [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions |
|
Date: |
Fri, 27 Mar 2020 17:06:48 -0700 |
|
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 |
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> +static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
> +{
> + uint64_t hi_64, lo_64, abs_s2 = s2;
> +
> + if (s2 < 0) {
> + abs_s2 = -s2;
> + }
> + mulu64(&lo_64, &hi_64, abs_s2, s1);
> + if (s2 < 0) {
> + lo_64 = ~lo_64;
> + hi_64 = ~hi_64;
> + if (lo_64 == UINT64_MAX) {
> + lo_64 = 0;
> + hi_64 += 1;
> + } else {
> + lo_64 += 1;
> + }
> + }
> +
> + return hi_64;
> +}
Missed the improvement here. See tcg_gen_mulsu2_i64.
Otherwise,
Reviewed-by: Richard Henderson <address@hidden>
r~
- [PATCH v6 14/61] target/riscv: vector single-width bit shift instructions, (continued)
- [PATCH v6 14/61] target/riscv: vector single-width bit shift instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 15/61] target/riscv: vector narrowing integer right shift instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 16/61] target/riscv: vector integer comparison instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 17/61] target/riscv: vector integer min/max instructions, LIU Zhiwei, 2020/03/17
- [PATCH v6 18/61] target/riscv: vector single-width integer multiply instructions, LIU Zhiwei, 2020/03/17
[PATCH v6 19/61] target/riscv: vector integer divide instructions, LIU Zhiwei, 2020/03/17
[PATCH v6 20/61] target/riscv: vector widening integer multiply instructions, LIU Zhiwei, 2020/03/17
[PATCH v6 21/61] target/riscv: vector single-width integer multiply-add instructions, LIU Zhiwei, 2020/03/17