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[PATCH v1 0/9] RISC-V Add the OpenTitan Machine
From: |
Alistair Francis |
Subject: |
[PATCH v1 0/9] RISC-V Add the OpenTitan Machine |
Date: |
Sat, 25 Apr 2020 04:28:57 -0700 |
From: Alistair Francis <address@hidden>
OpenTitan is an open source silicon Root of Trust (RoT) project. This
series adds initial support for the OpenTitan machine to QEMU.
This series add the Ibex CPU to the QEMU RISC-V target. It then adds the
OpenTitan machine, the Ibex UART and the Ibex PLIC.
The UART has been tested sending data, but not receiving as there is
currently no UART receiving support in Tock.
With this series QEMU can boot the OpenTitan ROM, Tock OS and a Tock
userspace app.
The Ibex PLIC is similar to the RISC-V PLIC (and is based on the QEMU
implementation) with some differences. The hope is that the Ibex PLIC
will converge to follow the RISC-V spec. As that happens I want to
update the QEMU Ibex PLIC and hopefully eventually replace the current
PLIC as the implementation is a little overlay complex.
For more details on OpenTitan, see here: https://docs.opentitan.org/
Alistair Francis (9):
riscv/boot: Add a missing header include
target/riscv: Don't overwrite the reset vector
target/riscv: Add the lowRISC Ibex CPU
riscv: Initial commit of OpenTitan machine
hw/char: Initial commit of Ibex UART
hw/intc: Initial commit of lowRISC Ibex PLIC
riscv/opentitan: Connect the PLIC device
riscv/opentitan: Connect the UART device
target/riscv: Use a smaller guess size for no-MMU PMP
MAINTAINERS | 14 +
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 11 +-
hw/char/Makefile.objs | 1 +
hw/char/ibex_uart.c | 487 ++++++++++++++++++++++++++++
hw/intc/Makefile.objs | 1 +
hw/intc/ibex_plic.c | 261 +++++++++++++++
hw/riscv/Kconfig | 9 +
hw/riscv/Makefile.objs | 1 +
hw/riscv/opentitan.c | 204 ++++++++++++
include/hw/char/ibex_uart.h | 110 +++++++
include/hw/intc/ibex_plic.h | 63 ++++
include/hw/riscv/boot.h | 1 +
include/hw/riscv/opentitan.h | 79 +++++
target/riscv/cpu.c | 30 +-
target/riscv/cpu.h | 1 +
target/riscv/pmp.c | 19 +-
17 files changed, 1278 insertions(+), 15 deletions(-)
create mode 100644 hw/char/ibex_uart.c
create mode 100644 hw/intc/ibex_plic.c
create mode 100644 hw/riscv/opentitan.c
create mode 100644 include/hw/char/ibex_uart.h
create mode 100644 include/hw/intc/ibex_plic.h
create mode 100644 include/hw/riscv/opentitan.h
--
2.26.2
- [PATCH v1 0/9] RISC-V Add the OpenTitan Machine,
Alistair Francis <=
- [PATCH v1 1/9] riscv/boot: Add a missing header include, Alistair Francis, 2020/04/26
- [PATCH v1 2/9] target/riscv: Don't overwrite the reset vector, Alistair Francis, 2020/04/26
- [PATCH v1 3/9] target/riscv: Add the lowRISC Ibex CPU, Alistair Francis, 2020/04/26
- [PATCH v1 5/9] hw/char: Initial commit of Ibex UART, Alistair Francis, 2020/04/26
- [PATCH v1 4/9] riscv: Initial commit of OpenTitan machine, Alistair Francis, 2020/04/26
- [PATCH v1 8/9] riscv/opentitan: Connect the UART device, Alistair Francis, 2020/04/26
- [PATCH v1 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC, Alistair Francis, 2020/04/26
- [PATCH v1 7/9] riscv/opentitan: Connect the PLIC device, Alistair Francis, 2020/04/26
- [PATCH v1 9/9] target/riscv: Use a smaller guess size for no-MMU PMP, Alistair Francis, 2020/04/26