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[PULL 04/31] bugfix: Use gicr_typer in arm_gicv3_icc_reset
From: |
Peter Maydell |
Subject: |
[PULL 04/31] bugfix: Use gicr_typer in arm_gicv3_icc_reset |
Date: |
Thu, 30 Apr 2020 12:51:15 +0100 |
From: Keqian Zhu <address@hidden>
The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer,
of which high 32bit is constructed by mp_affinity. For most case,
the high 32bit of mp_affinity is zero, so it will always access the
ICC_CTLR_EL1 of CPU0.
Signed-off-by: Keqian Zhu <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_kvm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 49304ca589d..ca43bf87cab 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -658,13 +658,11 @@ static void kvm_arm_gicv3_get(GICv3State *s)
static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
- ARMCPU *cpu;
GICv3State *s;
GICv3CPUState *c;
c = (GICv3CPUState *)env->gicv3state;
s = c->gic;
- cpu = ARM_CPU(c->cpu);
c->icc_pmr_el1 = 0;
c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
@@ -681,7 +679,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const
ARMCPRegInfo *ri)
/* Initialize to actual HW supported configuration */
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
- KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer),
&c->icc_ctlr_el1[GICV3_NS], false, &error_abort);
c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
--
2.20.1
- [PULL 00/31] target-arm queue, Peter Maydell, 2020/04/30
- [PULL 01/31] dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness, Peter Maydell, 2020/04/30
- [PULL 03/31] nrf51: Fix last GPIO CNF address, Peter Maydell, 2020/04/30
- [PULL 02/31] dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness, Peter Maydell, 2020/04/30
- [PULL 05/31] Typo: Correct the name of CPU hotplug memory region, Peter Maydell, 2020/04/30
- [PULL 04/31] bugfix: Use gicr_typer in arm_gicv3_icc_reset,
Peter Maydell <=
- [PULL 07/31] msf2: Add EMAC block to SmartFusion2 SoC, Peter Maydell, 2020/04/30
- [PULL 06/31] hw/net: Add Smartfusion2 emac block, Peter Maydell, 2020/04/30
- [PULL 08/31] tests/boot_linux_console: Add ethernet test to SmartFusion2, Peter Maydell, 2020/04/30
- [PULL 10/31] hw/core/clock-vmstate: define a vmstate entry for clock state, Peter Maydell, 2020/04/30
- [PULL 11/31] qdev: add clock input&output support to devices., Peter Maydell, 2020/04/30
- [PULL 12/31] qdev-clock: introduce an init array to ease the device construction, Peter Maydell, 2020/04/30
- [PULL 09/31] hw/core/clock: introduce clock object, Peter Maydell, 2020/04/30
- [PULL 13/31] docs/clocks: add device's clock documentation, Peter Maydell, 2020/04/30
- [PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts, Peter Maydell, 2020/04/30