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[PULL 38/45] target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same to dec
From: |
Peter Maydell |
Subject: |
[PULL 38/45] target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same to decodetree |
Date: |
Thu, 14 May 2020 15:21:31 +0100 |
Convert the Neon VQDMULH and VQRDMULH 3-reg-same insns to
decodetree. These are the last integer operations in the
3-reg-same group.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
target/arm/neon-dp.decode | 3 +++
target/arm/translate-neon.inc.c | 24 ++++++++++++++++++++++++
target/arm/translate.c | 24 +-----------------------
3 files changed, 28 insertions(+), 23 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index 3659fb036c7..fd32837fb17 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -152,6 +152,9 @@ VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0
.... @3same_q0
VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
+VQDMULH_3s 1111 001 0 0 . .. .... .... 1011 . . . 0 .... @3same
+VQRDMULH_3s 1111 001 1 0 . .. .... .... 1011 . . . 0 .... @3same
+
VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index e0137364075..f52302f42b1 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -997,3 +997,27 @@ DO_3SAME_PAIR(VPMIN_S, pmin_s)
DO_3SAME_PAIR(VPMAX_U, pmax_u)
DO_3SAME_PAIR(VPMIN_U, pmin_u)
DO_3SAME_PAIR(VPADD, padd_u)
+
+#define DO_3SAME_VQDMULH(INSN, FUNC) \
+ WRAP_ENV_FN(gen_##INSN##_tramp16, gen_helper_neon_##FUNC##_s16); \
+ WRAP_ENV_FN(gen_##INSN##_tramp32, gen_helper_neon_##FUNC##_s32); \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ static const GVecGen3 ops[2] = { \
+ { .fni4 = gen_##INSN##_tramp16 }, \
+ { .fni4 = gen_##INSN##_tramp32 }, \
+ }; \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, &ops[vece - 1]); \
+ } \
+ static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
+ { \
+ if (a->size != 1 && a->size != 2) { \
+ return false; \
+ } \
+ return do_3same(s, a, gen_##INSN##_3s); \
+ }
+
+DO_3SAME_VQDMULH(VQDMULH, qdmulh)
+DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ce30417014d..561cb67286d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5432,6 +5432,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t
insn)
case NEON_3R_VPMAX:
case NEON_3R_VPMIN:
case NEON_3R_VPADD_VQRDMLAH:
+ case NEON_3R_VQDMULH_VQRDMULH:
/* Already handled by decodetree */
return 1;
}
@@ -5496,29 +5497,6 @@ static int disas_neon_data_insn(DisasContext *s,
uint32_t insn)
tmp2 = neon_load_reg(rm, pass);
}
switch (op) {
- case NEON_3R_VQDMULH_VQRDMULH: /* Multiply high. */
- if (!u) { /* VQDMULH */
- switch (size) {
- case 1:
- gen_helper_neon_qdmulh_s16(tmp, cpu_env, tmp, tmp2);
- break;
- case 2:
- gen_helper_neon_qdmulh_s32(tmp, cpu_env, tmp, tmp2);
- break;
- default: abort();
- }
- } else { /* VQRDMULH */
- switch (size) {
- case 1:
- gen_helper_neon_qrdmulh_s16(tmp, cpu_env, tmp, tmp2);
- break;
- case 2:
- gen_helper_neon_qrdmulh_s32(tmp, cpu_env, tmp, tmp2);
- break;
- default: abort();
- }
- }
- break;
case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
--
2.20.1
- [PULL 22/45] ACPI: Build related register address fields via hardware error fw_cfg blob, (continued)
- [PULL 22/45] ACPI: Build related register address fields via hardware error fw_cfg blob, Peter Maydell, 2020/05/14
- [PULL 28/45] MAINTAINERS: Add ACPI/HEST/GHES entries, Peter Maydell, 2020/05/14
- [PULL 26/45] ACPI: Record Generic Error Status Block(GESB) table, Peter Maydell, 2020/05/14
- [PULL 29/45] target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH to decodetree, Peter Maydell, 2020/05/14
- [PULL 31/45] target/arm: Convert Neon 64-bit element 3-reg-same insns, Peter Maydell, 2020/05/14
- [PULL 33/45] target/arm: Convert Neon VABA/VABD 3-reg-same to decodetree, Peter Maydell, 2020/05/14
- [PULL 34/45] target/arm: Convert Neon VRHADD, VHSUB 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 35/45] target/arm: Convert Neon VQSHL, VRSHL, VQRSHL 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 32/45] target/arm: Convert Neon VHADD 3-reg-same insns, Peter Maydell, 2020/05/14
- [PULL 37/45] target/arm: Convert Neon VPADD 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 38/45] target/arm: Convert Neon VQDMULH/VQRDMULH 3-reg-same to decodetree,
Peter Maydell <=
- [PULL 39/45] target/arm: Convert Neon VADD, VSUB, VABD 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 36/45] target/arm: Convert Neon VPMAX/VPMIN 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 41/45] target/arm: Convert Neon fp VMUL, VMLA, VMLS 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 40/45] target/arm: Convert Neon VPMIN/VPMAX/VPADD float 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 42/45] target/arm: Convert Neon 3-reg-same compare insns to decodetree, Peter Maydell, 2020/05/14
- [PULL 43/45] target/arm: Move 'env' argument of recps_f32 and rsqrts_f32 helpers to usual place, Peter Maydell, 2020/05/14
- [PULL 44/45] target/arm: Convert Neon fp VMAX/VMIN/VMAXNM/VMINNM/VRECPS/VRSQRTS to decodetree, Peter Maydell, 2020/05/14
- [PULL 45/45] target/arm: Convert NEON VFMA, VFMS 3-reg-same insns to decodetree, Peter Maydell, 2020/05/14
- Re: [PULL 00/45] target-arm queue, Peter Maydell, 2020/05/14