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[PATCH v2 003/100] target/arm: Split out gen_gvec_fn_zz
From: |
Richard Henderson |
Subject: |
[PATCH v2 003/100] target/arm: Split out gen_gvec_fn_zz |
Date: |
Wed, 17 Jun 2020 21:25:07 -0700 |
Model the new function on gen_gvec_fn2 in translate-a64.c, but
indicating which kind of register and in which order. Since there
is only one user of do_vector2_z, fold it into do_mov_z.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index ac7b3119e5..bc286331cb 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -143,15 +143,13 @@ static int pred_gvec_reg_size(DisasContext *s)
}
/* Invoke a vector expander on two Zregs. */
-static bool do_vector2_z(DisasContext *s, GVecGen2Fn *gvec_fn,
- int esz, int rd, int rn)
+
+static void gen_gvec_fn_zz(DisasContext *s, GVecGen2Fn *gvec_fn,
+ int esz, int rd, int rn)
{
- if (sve_access_check(s)) {
- unsigned vsz = vec_full_reg_size(s);
- gvec_fn(esz, vec_full_reg_offset(s, rd),
- vec_full_reg_offset(s, rn), vsz, vsz);
- }
- return true;
+ unsigned vsz = vec_full_reg_size(s);
+ gvec_fn(esz, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn), vsz, vsz);
}
/* Invoke a vector expander on three Zregs. */
@@ -170,7 +168,10 @@ static bool do_vector3_z(DisasContext *s, GVecGen3Fn
*gvec_fn,
/* Invoke a vector move on two Zregs. */
static bool do_mov_z(DisasContext *s, int rd, int rn)
{
- return do_vector2_z(s, tcg_gen_gvec_mov, 0, rd, rn);
+ if (sve_access_check(s)) {
+ gen_gvec_fn_zz(s, tcg_gen_gvec_mov, MO_8, rd, rn);
+ }
+ return true;
}
/* Initialize a Zreg with replications of a 64-bit immediate. */
--
2.25.1
- [PATCH v2 000/100] target/arm: Implement SVE2, Richard Henderson, 2020/06/18
- [PATCH v2 002/100] qemu/int128: Add int128_lshift, Richard Henderson, 2020/06/18
- [PATCH v2 001/100] tcg: Save/restore vecop_list around minmax fallback, Richard Henderson, 2020/06/18
- [PATCH v2 003/100] target/arm: Split out gen_gvec_fn_zz,
Richard Henderson <=
- [PATCH v2 004/100] target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn, Richard Henderson, 2020/06/18
- [PATCH v2 005/100] target/arm: Rearrange {sve, fp}_check_access assert, Richard Henderson, 2020/06/18
- [PATCH v2 006/100] target/arm: Merge do_vector2_p into do_mov_p, Richard Henderson, 2020/06/18
- [PATCH v2 007/100] target/arm: Clean up 4-operand predicate expansion, Richard Henderson, 2020/06/18
- [PATCH v2 008/100] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp, Richard Henderson, 2020/06/18
- [PATCH v2 009/100] target/arm: Split out gen_gvec_ool_zzzp, Richard Henderson, 2020/06/18
- [PATCH v2 010/100] target/arm: Merge helper_sve_clr_* and helper_sve_movz_*, Richard Henderson, 2020/06/18
- [PATCH v2 013/100] target/arm: Split out gen_gvec_ool_zz, Richard Henderson, 2020/06/18
- [PATCH v2 011/100] target/arm: Split out gen_gvec_ool_zzp, Richard Henderson, 2020/06/18
- [PATCH v2 012/100] target/arm: Split out gen_gvec_ool_zzz, Richard Henderson, 2020/06/18