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[PULL 13/57] target/arm: Add isar tests for mte
From: |
Peter Maydell |
Subject: |
[PULL 13/57] target/arm: Add isar tests for mte |
Date: |
Fri, 26 Jun 2020 16:13:40 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index cf66b8c7fb0..ff70115801f 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3814,6 +3814,16 @@ static inline bool isar_feature_aa64_bti(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
}
+static inline bool isar_feature_aa64_mte_insn_reg(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) != 0;
+}
+
+static inline bool isar_feature_aa64_mte(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, MTE) >= 2;
+}
+
static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 &&
--
2.20.1
- [PULL 06/57] hw/misc/pca9552: Rename generic code as pca955x, (continued)
- [PULL 06/57] hw/misc/pca9552: Rename generic code as pca955x, Peter Maydell, 2020/06/26
- [PULL 09/57] hw/misc/pca9552: Trace GPIO High/Low events, Peter Maydell, 2020/06/26
- [PULL 07/57] hw/misc/pca9552: Add generic PCA955xClass, parent of TYPE_PCA9552, Peter Maydell, 2020/06/26
- [PULL 08/57] hw/misc/pca9552: Add a 'description' property for debugging purpose, Peter Maydell, 2020/06/26
- [PULL 12/57] hw/misc/pca9552: Model qdev output GPIOs, Peter Maydell, 2020/06/26
- [PULL 10/57] hw/arm/aspeed: Describe each PCA9552 device, Peter Maydell, 2020/06/26
- [PULL 11/57] hw/misc/pca9552: Trace GPIO change events, Peter Maydell, 2020/06/26
- [PULL 15/57] target/arm: Add support for MTE to SCTLR_ELx, Peter Maydell, 2020/06/26
- [PULL 14/57] target/arm: Improve masking of SCR RES0 bits, Peter Maydell, 2020/06/26
- [PULL 16/57] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Peter Maydell, 2020/06/26
- [PULL 13/57] target/arm: Add isar tests for mte,
Peter Maydell <=
- [PULL 17/57] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Peter Maydell, 2020/06/26
- [PULL 21/57] target/arm: Implement the IRG instruction, Peter Maydell, 2020/06/26
- [PULL 18/57] target/arm: Add DISAS_UPDATE_NOCHAIN, Peter Maydell, 2020/06/26
- [PULL 19/57] target/arm: Add MTE system registers, Peter Maydell, 2020/06/26
- [PULL 20/57] target/arm: Add MTE bits to tb_flags, Peter Maydell, 2020/06/26
- [PULL 24/57] target/arm: Implement the GMI instruction, Peter Maydell, 2020/06/26
- [PULL 22/57] target/arm: Revise decoding for disas_add_sub_imm, Peter Maydell, 2020/06/26
- [PULL 23/57] target/arm: Implement the ADDG, SUBG instructions, Peter Maydell, 2020/06/26
- [PULL 25/57] target/arm: Implement the SUBP instruction, Peter Maydell, 2020/06/26
- [PULL 26/57] target/arm: Define arm_cpu_do_unaligned_access for user-only, Peter Maydell, 2020/06/26