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[PULL 14/57] target/arm: Improve masking of SCR RES0 bits
From: |
Peter Maydell |
Subject: |
[PULL 14/57] target/arm: Improve masking of SCR RES0 bits |
Date: |
Fri, 26 Jun 2020 16:13:41 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 972a7667309..a29f0a28d84 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2011,9 +2011,16 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
uint32_t valid_mask = 0x3fff;
ARMCPU *cpu = env_archcpu(env);
- if (arm_el_is_aa64(env, 3)) {
+ if (ri->state == ARM_CP_STATE_AA64) {
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
valid_mask &= ~SCR_NET;
+
+ if (cpu_isar_feature(aa64_lor, cpu)) {
+ valid_mask |= SCR_TLOR;
+ }
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
+ valid_mask |= SCR_API | SCR_APK;
+ }
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
}
@@ -2032,12 +2039,6 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
valid_mask &= ~SCR_SMD;
}
}
- if (cpu_isar_feature(aa64_lor, cpu)) {
- valid_mask |= SCR_TLOR;
- }
- if (cpu_isar_feature(aa64_pauth, cpu)) {
- valid_mask |= SCR_API | SCR_APK;
- }
/* Clear all-context RES0 bits. */
value &= valid_mask;
--
2.20.1
- [PULL 05/57] hw/misc/pca9552: Rename 'nr_leds' as 'pin_count', (continued)
- [PULL 05/57] hw/misc/pca9552: Rename 'nr_leds' as 'pin_count', Peter Maydell, 2020/06/26
- [PULL 04/57] hw/i2c/core: Add i2c_try_create_slave() and i2c_realize_and_unref(), Peter Maydell, 2020/06/26
- [PULL 06/57] hw/misc/pca9552: Rename generic code as pca955x, Peter Maydell, 2020/06/26
- [PULL 09/57] hw/misc/pca9552: Trace GPIO High/Low events, Peter Maydell, 2020/06/26
- [PULL 07/57] hw/misc/pca9552: Add generic PCA955xClass, parent of TYPE_PCA9552, Peter Maydell, 2020/06/26
- [PULL 08/57] hw/misc/pca9552: Add a 'description' property for debugging purpose, Peter Maydell, 2020/06/26
- [PULL 12/57] hw/misc/pca9552: Model qdev output GPIOs, Peter Maydell, 2020/06/26
- [PULL 10/57] hw/arm/aspeed: Describe each PCA9552 device, Peter Maydell, 2020/06/26
- [PULL 11/57] hw/misc/pca9552: Trace GPIO change events, Peter Maydell, 2020/06/26
- [PULL 15/57] target/arm: Add support for MTE to SCTLR_ELx, Peter Maydell, 2020/06/26
- [PULL 14/57] target/arm: Improve masking of SCR RES0 bits,
Peter Maydell <=
- [PULL 16/57] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3, Peter Maydell, 2020/06/26
- [PULL 13/57] target/arm: Add isar tests for mte, Peter Maydell, 2020/06/26
- [PULL 17/57] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT, Peter Maydell, 2020/06/26
- [PULL 21/57] target/arm: Implement the IRG instruction, Peter Maydell, 2020/06/26
- [PULL 18/57] target/arm: Add DISAS_UPDATE_NOCHAIN, Peter Maydell, 2020/06/26
- [PULL 19/57] target/arm: Add MTE system registers, Peter Maydell, 2020/06/26
- [PULL 20/57] target/arm: Add MTE bits to tb_flags, Peter Maydell, 2020/06/26
- [PULL 24/57] target/arm: Implement the GMI instruction, Peter Maydell, 2020/06/26
- [PULL 22/57] target/arm: Revise decoding for disas_add_sub_imm, Peter Maydell, 2020/06/26
- [PULL 23/57] target/arm: Implement the ADDG, SUBG instructions, Peter Maydell, 2020/06/26