Re: [PULL 00/57] target-arm queue

[no-reply]

Patchew URL: 
20200626151424.30117-1-peter.maydell@linaro.org/">https://patchew.org/QEMU/20200626151424.30117-1-peter.maydell@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL 00/57] target-arm queue
Type: series
Message-id: 20200626151424.30117-1-peter.maydell@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
   10f7ffa..87fb952  master     -> master
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/20200626151424.30117-1-peter.maydell@linaro.org -> 
patchew/20200626151424.30117-1-peter.maydell@linaro.org
Switched to a new branch 'test'
b53e5c7 target/arm: Enable MTE
10b49a9 target/arm: Add allocation tag storage for system mode
7677cba target/arm: Create tagged ram when MTE is enabled
39aaf61 target/arm: Cache the Tagged bit for a page in MemTxAttrs
4c74a57 target/arm: Always pass cacheattr to get_phys_addr
55df5a9 target/arm: Set PSTATE.TCO on exception entry
19ca978 target/arm: Implement data cache set allocation tags
fd125b3 target/arm: Complete TBI clearing for user-only for SVE
a1eb002 target/arm: Add mte helpers for sve scatter/gather memory ops
1aed563 target/arm: Handle TBI for sve scalar + int memory ops
f37dfeb target/arm: Add mte helpers for sve scalar + int ff/nf loads
30839ff target/arm: Add mte helpers for sve scalar + int stores
4731ba2 target/arm: Add mte helpers for sve scalar + int loads
7e55cab target/arm: Add arm_tlb_bti_gp
7575129 target/arm: Tidy trans_LD1R_zpri
ff3bf83 target/arm: Use mte_check1 for sve LD1R
a629a5f target/arm: Use mte_checkN for sve unpredicated stores
6f75c45 target/arm: Use mte_checkN for sve unpredicated loads
936cb9e target/arm: Add helper_mte_check_zva
af54555 target/arm: Implement helper_mte_checkN
c7b59cf target/arm: Implement helper_mte_check1
9940098 target/arm: Add gen_mte_checkN
7426d45 target/arm: Add gen_mte_check1
c286366 target/arm: Move regime_tcr to internals.h
6865cad target/arm: Move regime_el to internals.h
f10b017 target/arm: Implement the access tag cache flushes
a837151 target/arm: Implement the LDGM, STGM, STZGM instructions
8140eaf target/arm: Simplify DC_ZVA
12dc451 target/arm: Restrict the values of DCZID.BS under TCG
2f19384 target/arm: Implement the STGP instruction
6c0963f target/arm: Implement LDG, STG, ST2G instructions
226cace target/arm: Define arm_cpu_do_unaligned_access for user-only
cecc01a target/arm: Implement the SUBP instruction
af547f0 target/arm: Implement the GMI instruction
08add27 target/arm: Implement the ADDG, SUBG instructions
c64de43 target/arm: Revise decoding for disas_add_sub_imm
c16250e target/arm: Implement the IRG instruction
1a63093 target/arm: Add MTE bits to tb_flags
35c5ce6 target/arm: Add MTE system registers
2691dfb target/arm: Add DISAS_UPDATE_NOCHAIN
96491ca target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT
05038d1 target/arm: Add support for MTE to HCR_EL2 and SCR_EL3
0014bb4 target/arm: Add support for MTE to SCTLR_ELx
4a1aa57 target/arm: Improve masking of SCR RES0 bits
9d02d26 target/arm: Add isar tests for mte
ed5c901 hw/misc/pca9552: Model qdev output GPIOs
ea7aa75 hw/misc/pca9552: Trace GPIO change events
1f0e0c1 hw/arm/aspeed: Describe each PCA9552 device
205db39 hw/misc/pca9552: Trace GPIO High/Low events
9c4f8d3 hw/misc/pca9552: Add a 'description' property for debugging purpose
c3f2935 hw/misc/pca9552: Add generic PCA955xClass, parent of TYPE_PCA9552
64d28e2 hw/misc/pca9552: Rename generic code as pca955x
070bfd9 hw/misc/pca9552: Rename 'nr_leds' as 'pin_count'
fd78e0f hw/i2c/core: Add i2c_try_create_slave() and i2c_realize_and_unref()
5a5e9a8 hw/arm/aspeed: QOM'ify AspeedMachineState
017b699 hw/arm/aspeed: Rename AspeedBoardState as AspeedMachineState
8270190 hw/arm/aspeed: Remove extraneous MemoryRegion object owner

=== OUTPUT BEGIN ===
1/57 Checking commit 82701909ccd7 (hw/arm/aspeed: Remove extraneous 
MemoryRegion object owner)
2/57 Checking commit 017b6996191b (hw/arm/aspeed: Rename AspeedBoardState as 
AspeedMachineState)
3/57 Checking commit 5a5e9a845833 (hw/arm/aspeed: QOM'ify AspeedMachineState)
4/57 Checking commit fd78e0fd9a27 (hw/i2c/core: Add i2c_try_create_slave() and 
i2c_realize_and_unref())
5/57 Checking commit 070bfd913405 (hw/misc/pca9552: Rename 'nr_leds' as 
'pin_count')
6/57 Checking commit 64d28e279fdf (hw/misc/pca9552: Rename generic code as 
pca955x)
7/57 Checking commit c3f29356b861 (hw/misc/pca9552: Add generic PCA955xClass, 
parent of TYPE_PCA9552)
8/57 Checking commit 9c4f8d32b106 (hw/misc/pca9552: Add a 'description' 
property for debugging purpose)
9/57 Checking commit 205db39d5fb2 (hw/misc/pca9552: Trace GPIO High/Low events)
10/57 Checking commit 1f0e0c125e8f (hw/arm/aspeed: Describe each PCA9552 device)
11/57 Checking commit ea7aa752e056 (hw/misc/pca9552: Trace GPIO change events)
12/57 Checking commit ed5c901cfdeb (hw/misc/pca9552: Model qdev output GPIOs)
13/57 Checking commit 9d02d26c56ad (target/arm: Add isar tests for mte)
14/57 Checking commit 4a1aa572b161 (target/arm: Improve masking of SCR RES0 
bits)
15/57 Checking commit 0014bb4e011a (target/arm: Add support for MTE to 
SCTLR_ELx)
16/57 Checking commit 05038d1ecae1 (target/arm: Add support for MTE to HCR_EL2 
and SCR_EL3)
17/57 Checking commit 96491ca17630 (target/arm: Rename DISAS_UPDATE to 
DISAS_UPDATE_EXIT)
18/57 Checking commit 2691dfb7198a (target/arm: Add DISAS_UPDATE_NOCHAIN)
19/57 Checking commit 35c5ce6272c4 (target/arm: Add MTE system registers)
20/57 Checking commit 1a6309381c33 (target/arm: Add MTE bits to tb_flags)
21/57 Checking commit c16250ee319e (target/arm: Implement the IRG instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 120 lines checked

Patch 21/57 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/57 Checking commit c64de439219f (target/arm: Revise decoding for 
disas_add_sub_imm)
23/57 Checking commit 08add27b90eb (target/arm: Implement the ADDG, SUBG 
instructions)
24/57 Checking commit af547f0081fe (target/arm: Implement the GMI instruction)
25/57 Checking commit cecc01a646bb (target/arm: Implement the SUBP instruction)
26/57 Checking commit 226cace966c3 (target/arm: Define 
arm_cpu_do_unaligned_access for user-only)
27/57 Checking commit 6c0963fa172d (target/arm: Implement LDG, STG, ST2G 
instructions)
28/57 Checking commit 2f193847ad59 (target/arm: Implement the STGP instruction)
29/57 Checking commit 12dc451f60c9 (target/arm: Restrict the values of DCZID.BS 
under TCG)
30/57 Checking commit 8140eaff6c6b (target/arm: Simplify DC_ZVA)
31/57 Checking commit a83715146bc6 (target/arm: Implement the LDGM, STGM, STZGM 
instructions)
32/57 Checking commit f10b017ccbdb (target/arm: Implement the access tag cache 
flushes)
33/57 Checking commit 6865cade8c23 (target/arm: Move regime_el to internals.h)
34/57 Checking commit c286366840ff (target/arm: Move regime_tcr to internals.h)
35/57 Checking commit 7426d4551c83 (target/arm: Add gen_mte_check1)
36/57 Checking commit 9940098d133a (target/arm: Add gen_mte_checkN)
37/57 Checking commit c7b59cfedda1 (target/arm: Implement helper_mte_check1)
38/57 Checking commit af545558b63b (target/arm: Implement helper_mte_checkN)
39/57 Checking commit 936cb9e4335a (target/arm: Add helper_mte_check_zva)
40/57 Checking commit 6f75c45de7e8 (target/arm: Use mte_checkN for sve 
unpredicated loads)
41/57 Checking commit a629a5f71cfd (target/arm: Use mte_checkN for sve 
unpredicated stores)
42/57 Checking commit ff3bf8368e05 (target/arm: Use mte_check1 for sve LD1R)
43/57 Checking commit 7575129a8fbe (target/arm: Tidy trans_LD1R_zpri)
44/57 Checking commit 7e55cab7804c (target/arm: Add arm_tlb_bti_gp)
45/57 Checking commit 4731ba20b5b6 (target/arm: Add mte helpers for sve scalar 
+ int loads)
46/57 Checking commit 30839ff5f169 (target/arm: Add mte helpers for sve scalar 
+ int stores)
47/57 Checking commit f37dfeb64845 (target/arm: Add mte helpers for sve scalar 
+ int ff/nf loads)
48/57 Checking commit 1aed5630dfb6 (target/arm: Handle TBI for sve scalar + int 
memory ops)
49/57 Checking commit a1eb002db49c (target/arm: Add mte helpers for sve 
scatter/gather memory ops)
50/57 Checking commit fd125b3a4f5a (target/arm: Complete TBI clearing for 
user-only for SVE)
ERROR: spaces required around that '*' (ctx:VxV)
#59: FILE: target/arm/sve_helper.c:3978:
+        (TYPEM)*(TYPEE *)(vd + H(reg_off)), ra);                            \
                ^

total: 1 errors, 0 warnings, 57 lines checked

Patch 50/57 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

51/57 Checking commit 19ca9785c408 (target/arm: Implement data cache set 
allocation tags)
52/57 Checking commit 55df5a9193e1 (target/arm: Set PSTATE.TCO on exception 
entry)
53/57 Checking commit 4c74a5704b2f (target/arm: Always pass cacheattr to 
get_phys_addr)
54/57 Checking commit 39aaf61493df (target/arm: Cache the Tagged bit for a page 
in MemTxAttrs)
55/57 Checking commit 7677cba0a102 (target/arm: Create tagged ram when MTE is 
enabled)
56/57 Checking commit 10b49a9870df (target/arm: Add allocation tag storage for 
system mode)
57/57 Checking commit b53e5c7b707a (target/arm: Enable MTE)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
20200626151424.30117-1-peter.maydell@linaro.org/testing.checkpatch/?type=message">http://patchew.org/logs/20200626151424.30117-1-peter.maydell@linaro.org/testing.checkpatch/?type=message.
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