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Re: [PATCH v2] timer: Handle decrements of PIT counter
From: |
Kevin O'Connor |
Subject: |
Re: [PATCH v2] timer: Handle decrements of PIT counter |
Date: |
Fri, 26 Jun 2020 14:27:13 -0400 |
On Fri, Jun 26, 2020 at 09:06:58PM +0300, Roman Bolshakov wrote:
> There's a fallback to PIT if TSC is not present but it doesn't work
> properly. It prevents boot from floppy on isapc and 486 cpu [1][2].
>
> SeaBIOS configures PIT in Mode 2. PIT counter is decremented in the mode
> but timer_adjust_bits() thinks that the counter overflows and increases
> 32-bit tick counter on each detected "overflow". Invalid overflow
> detection results in 55ms time advance (1 / 18.2Hz) on each read from
> PIT counter. So all timers expire much faster and 5-second floppy
> timeout expires in 83 real microseconds (or just a bit longer).
>
> It can be fixed by making the counter recieved from PIT an increasing
> value so it can be passed to timer_adjust_bits():
> 0, 1, 2 and up to 65535 and then the counter is re-loaded with 0.
>
> 1. https://bugs.launchpad.net/seabios/+bug/1840719
> 2. https://lists.gnu.org/archive/html/qemu-devel/2019-08/msg03924.html
Thanks. I committed this change.
-Kevin