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[PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies |
Date: |
Sat, 17 Oct 2020 16:02:19 +0200 |
Use the Clock API and let the CPU object have an input clock.
If no clock is connected, keep using the default frequency of
200 MHz used since the introduction of the 'r4k' machine in
commit 6af0bf9c7c3.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201012095804.3335117-12-f4bug@amsat.org>
---
target/mips/cpu.h | 4 ++++
target/mips/cpu.c | 11 +++++++++--
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index baeceb892ef..062a4ba6225 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -4,6 +4,7 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
+#include "hw/clock.h"
#include "mips-defs.h"
#define TCG_GUEST_DEFAULT_MO (0)
@@ -1151,6 +1152,8 @@ struct CPUMIPSState {
/**
* MIPSCPU:
* @env: #CPUMIPSState
+ * @clock: this CPU input clock (may be connected
+ * to an output clock from another device).
* @cp0_count_rate: rate at which the coprocessor 0 counter increments
*
* A MIPS CPU.
@@ -1160,6 +1163,7 @@ struct MIPSCPU {
CPUState parent_obj;
/*< public >*/
+ Clock *clock;
CPUNegativeOffsetState neg;
CPUMIPSState env;
/*
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 461edfe22b7..2a6f4840e20 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -27,6 +27,7 @@
#include "sysemu/kvm.h"
#include "exec/exec-all.h"
#include "hw/qdev-properties.h"
+#include "hw/qdev-clock.h"
static void mips_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -144,8 +145,9 @@ static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
- env->cp0_count_ns = muldiv64(NANOSECONDS_PER_SECOND, cpu->cp0_count_rate,
- CPU_FREQ_HZ_DEFAULT);
+ env->cp0_count_ns = cpu->cp0_count_rate
+ * clock_get_ns(MIPS_CPU(cpu)->clock);
+ assert(env->cp0_count_ns);
}
static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
@@ -155,6 +157,10 @@ static void mips_cpu_realizefn(DeviceState *dev, Error
**errp)
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
Error *local_err = NULL;
+ if (!clock_get(cpu->clock)) {
+ /* Initialize the frequency in case the clock remains unconnected. */
+ clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT);
+ }
mips_cp0_period_set(cpu);
cpu_exec_realizefn(cs, &local_err);
@@ -178,6 +184,7 @@ static void mips_cpu_initfn(Object *obj)
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj);
cpu_set_cpustate_pointers(cpu);
+ cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu);
env->cpu_model = mcc->cpu_def;
}
--
2.26.2
- [PULL 12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op, (continued)
- [PULL 12/44] target/mips/op_helper: Document Invalidate/Writeback opcodes as no-op, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 08/44] target/mips: Add loongson-ext lswc2 group of instructions (Part 1), Philippe Mathieu-Daudé, 2020/10/17
- [PULL 10/44] target/mips: Add loongson-ext lsdc2 group of instructions, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 13/44] target/mips/op_helper: Log unimplemented cache opcode, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 14/44] target/mips: Move cpu_mips_get_random() with CP0 helpers, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 15/44] target/mips/cp0_timer: Explicit unit in variable name, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 16/44] target/mips/cp0_timer: Document TIMER_PERIOD origin, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 17/44] target/mips: Move cp0_count_ns to CPUMIPSState, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 18/44] target/mips/cpu: Calculate the CP0 timer period using the CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 19/44] target/mips/cpu: Make cp0_count_rate a property, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 20/44] target/mips/cpu: Allow the CPU to use dynamic frequencies,
Philippe Mathieu-Daudé <=
- [PULL 21/44] target/mips/cpu: Introduce mips_cpu_create_with_clock() helper, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 22/44] hw/mips/r4k: Explicit CPU frequency is 200 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 23/44] hw/mips/fuloong2e: Set CPU frequency to 533 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 24/44] hw/mips/mipssim: Correct CPU frequency, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 25/44] hw/mips/jazz: Correct CPU frequencies, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 26/44] hw/mips/cps: Expose input clock and connect it to CPU cores, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 27/44] hw/mips/boston: Set CPU frequency to 1 GHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 28/44] hw/mips/malta: Set CPU frequency to 320 MHz, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 29/44] hw/mips/cps: Do not allow use without input clock, Philippe Mathieu-Daudé, 2020/10/17
- [PULL 30/44] target/mips/cpu: Display warning when CPU is used without input clock, Philippe Mathieu-Daudé, 2020/10/17