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[PATCH 0/4] riscv: Add semihosting support [v10]
From: |
Keith Packard |
Subject: |
[PATCH 0/4] riscv: Add semihosting support [v10] |
Date: |
Mon, 26 Oct 2020 14:28:49 -0700 |
This series first adapts the existing ARM semihosting code to be
architecture-neutral, then adds RISC-V semihosting support using that.
Patch 1/4 moves the ARM semihosting support code to common directories and
adapts the build system to match.
Patch 2/4 changes the public API to this code to use
architecture-independent names and types.
Patch 3/4 changes the internals of this code to use architecture
neutral types where practical, and adds helper functions to abstract
away the architecture-specific details.
Patch 4/4 adds the RISC-V support, including modifying the breakpoint
handling code to recognize a semihosting sequence and adding RISC-V
specific implementations of the helper functions.
- [PATCH 0/4] riscv: Add semihosting support [v10],
Keith Packard <=
[PATCH 2/4] semihosting: Change common-semi API to be architecture-independent, Keith Packard, 2020/10/26
[PATCH 3/4] semihosting: Change internal common-semi interfaces to use CPUState *, Keith Packard, 2020/10/26