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[PULL v2 19/19] target/riscv/csr.c : add space before the open parenthes
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From: |
Alistair Francis |
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Subject: |
[PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(' |
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Date: |
Tue, 3 Nov 2020 07:21:50 -0800 |
From: Xinhao Zhang <zhangxinhao1@huawei.com>
Fix code style. Space required before the open parenthesis '('.
Signed-off-by: Xinhao Zhang <zhangxinhao1@huawei.com>
Signed-off-by: Kai Deng <dengkai1@huawei.com>
Reported-by: Euler Robot <euler.robot@huawei.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201030004815.4172849-1-zhangxinhao1@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e33f6cdc11..93263f8e06 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -882,7 +882,7 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return -RISCV_EXCP_ILLEGAL_INST;
} else {
- if((val ^ env->satp) & SATP_ASID) {
+ if ((val ^ env->satp) & SATP_ASID) {
tlb_flush(env_cpu(env));
}
env->satp = val;
--
2.28.0
- [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, (continued)
- [PULL v2 09/19] hw/riscv: microchip_pfsoc: Document where to look at the SoC memory maps, Alistair Francis, 2020/11/03
- [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/11/03
- [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Alistair Francis, 2020/11/03
- [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/11/03
- [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Alistair Francis, 2020/11/03
- [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/11/03
- [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/11/03
- [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Alistair Francis, 2020/11/03
- [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map, Alistair Francis, 2020/11/03
- [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Alistair Francis, 2020/11/03
- [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(',
Alistair Francis <=
- Re: [PULL v2 00/19] riscv-to-apply queue, Peter Maydell, 2020/11/03