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Re: [PULL v2 00/19] riscv-to-apply queue
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From: |
Peter Maydell |
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Subject: |
Re: [PULL v2 00/19] riscv-to-apply queue |
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Date: |
Tue, 3 Nov 2020 21:07:41 +0000 |
On Tue, 3 Nov 2020 at 15:33, Alistair Francis <alistair.francis@wdc.com> wrote:
>
> The following changes since commit 83851c7c60c90e9fb6a23ff48076387a77bc33cd:
>
> Merge remote-tracking branch
> 'remotes/mdroth/tags/qga-pull-2020-10-27-v3-tag' into staging (2020-11-03
> 12:47:58 +0000)
>
> are available in the Git repository at:
>
> git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20201103
>
> for you to fetch changes up to 422819776101520cb56658ee5facf926526cf870:
>
> target/riscv/csr.c : add space before the open parenthesis '(' (2020-11-03
> 07:17:23 -0800)
>
> ----------------------------------------------------------------
> This series adds support for migration to RISC-V QEMU and expands the
> Microchip PFSoC to allow unmodified HSS and Linux boots.
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
- [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, (continued)
- [PULL v2 10/19] hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support, Alistair Francis, 2020/11/03
- [PULL v2 11/19] hw/riscv: microchip_pfsoc: Connect DDR memory controller modules, Alistair Francis, 2020/11/03
- [PULL v2 12/19] hw/misc: Add Microchip PolarFire SoC IOSCB module support, Alistair Francis, 2020/11/03
- [PULL v2 13/19] hw/riscv: microchip_pfsoc: Connect the IOSCB module, Alistair Francis, 2020/11/03
- [PULL v2 14/19] hw/misc: Add Microchip PolarFire SoC SYSREG module support, Alistair Francis, 2020/11/03
- [PULL v2 15/19] hw/riscv: microchip_pfsoc: Connect the SYSREG module, Alistair Francis, 2020/11/03
- [PULL v2 16/19] hw/riscv: microchip_pfsoc: Map the reserved memory at address 0, Alistair Francis, 2020/11/03
- [PULL v2 17/19] hw/riscv: microchip_pfsoc: Correct DDR memory map, Alistair Francis, 2020/11/03
- [PULL v2 18/19] hw/riscv: microchip_pfsoc: Hook the I2C1 controller, Alistair Francis, 2020/11/03
- [PULL v2 19/19] target/riscv/csr.c : add space before the open parenthesis '(', Alistair Francis, 2020/11/03
- Re: [PULL v2 00/19] riscv-to-apply queue,
Peter Maydell <=