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[PULL 1/6] target/riscv: Add a virtualised MMU Mode
From: |
Alistair Francis |
Subject: |
[PULL 1/6] target/riscv: Add a virtualised MMU Mode |
Date: |
Mon, 9 Nov 2020 19:56:58 -0800 |
Add a new MMU mode that includes the current virt mode.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id:
4b301bc0ea36da962fc1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com
---
target/riscv/cpu-param.h | 11 ++++++++++-
target/riscv/cpu.h | 4 +++-
target/riscv/cpu_helper.c | 2 +-
3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 664fc1d371..80eb615f93 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -18,6 +18,15 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
-#define NB_MMU_MODES 4
+/*
+ * The current MMU Modes are:
+ * - U mode 0b000
+ * - S mode 0b001
+ * - M mode 0b011
+ * - U mode HLV/HLVX/HSV 0b100
+ * - S mode HLV/HLVX/HSV 0b101
+ * - M mode HLV/HLVX/HSV 0b111
+ */
+#define NB_MMU_MODES 8
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 87b68affa8..5d8e54c426 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -363,7 +363,9 @@ void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
-#define TB_FLAGS_MMU_MASK 3
+#define TB_FLAGS_MMU_MASK 7
+#define TB_FLAGS_PRIV_MMU_MASK 3
+#define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2)
#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
typedef CPURISCVState CPUArchState;
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3eb3a034db..9dfa7af401 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -323,7 +323,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr
*physical,
* (riscv_cpu_do_interrupt) is correct */
MemTxResult res;
MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- int mode = mmu_idx;
+ int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK;
bool use_background = false;
/*
--
2.29.2
- [PULL 0/6] riscv-to-apply queue, Alistair Francis, 2020/11/09
- [PULL 1/6] target/riscv: Add a virtualised MMU Mode,
Alistair Francis <=
- [PULL 2/6] target/riscv: Set the virtualised MMU mode when doing hyp accesses, Alistair Francis, 2020/11/09
- [PULL 3/6] target/riscv: Remove the HS_TWO_STAGE flag, Alistair Francis, 2020/11/09
- [PULL 4/6] target/riscv: Remove the hyp load and store functions, Alistair Francis, 2020/11/09
- [PULL 5/6] target/riscv: Split the Hypervisor execute load helpers, Alistair Francis, 2020/11/09
- [PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read, Alistair Francis, 2020/11/09
- Re: [PULL 0/6] riscv-to-apply queue, Alistair Francis, 2020/11/09
- Re: [PULL 0/6] riscv-to-apply queue, Peter Maydell, 2020/11/10