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[PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read
From: |
Alistair Francis |
Subject: |
[PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read |
Date: |
Mon, 9 Nov 2020 19:57:03 -0800 |
After claiming the interrupt by reading the claim register we want to
clear the register to make sure the interrupt doesn't appear at the next
read.
This matches the documentation for the claim register as when an interrupt
is claimed by a target the relevant bit of IP is cleared (which we already
do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
This also matches the current hardware.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id:
68d4575deef2559b7a747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com
---
hw/intc/ibex_plic.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index f49fa67c91..235e6b88ff 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
/* Return the current claimed interrupt */
ret = s->claim;
+ /* Clear the claimed interrupt */
+ s->claim = 0x00000000;
+
/* Update the interrupt status after the claim */
ibex_plic_update(s);
}
--
2.29.2
- [PULL 0/6] riscv-to-apply queue, Alistair Francis, 2020/11/09
- [PULL 1/6] target/riscv: Add a virtualised MMU Mode, Alistair Francis, 2020/11/09
- [PULL 2/6] target/riscv: Set the virtualised MMU mode when doing hyp accesses, Alistair Francis, 2020/11/09
- [PULL 3/6] target/riscv: Remove the HS_TWO_STAGE flag, Alistair Francis, 2020/11/09
- [PULL 4/6] target/riscv: Remove the hyp load and store functions, Alistair Francis, 2020/11/09
- [PULL 5/6] target/riscv: Split the Hypervisor execute load helpers, Alistair Francis, 2020/11/09
- [PULL 6/6] hw/intc/ibex_plic: Clear the claim register when read,
Alistair Francis <=
- Re: [PULL 0/6] riscv-to-apply queue, Alistair Francis, 2020/11/09
- Re: [PULL 0/6] riscv-to-apply queue, Peter Maydell, 2020/11/10