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[PATCH 01/17] target/mips: Introduce ase_msa_available() helper
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 01/17] target/mips: Introduce ase_msa_available() helper |
Date: |
Tue, 8 Dec 2020 01:36:46 +0100 |
Instead of accessing CP0_Config3 directly and checking
the 'MSA Present' bit, introduce an explicit helper,
making the code easier to read.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 6 ++++++
target/mips/kvm.c | 12 ++++++------
target/mips/translate.c | 8 +++-----
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 7b3ff2fd6fb..6d4c8d63930 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1296,6 +1296,12 @@ int cpu_mips_signal_handler(int host_signum, void
*pinfo, void *puc);
bool cpu_supports_cps_smp(const char *cpu_type);
bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
+/* Check presence of MSA implementation */
+static inline bool ase_msa_available(CPUMIPSState *env)
+{
+ return env->CP0_Config3 & (1 << CP0C3_MSAP);
+}
+
/* Check presence of multi-threading ASE implementation */
static inline bool ase_mt_available(CPUMIPSState *env)
{
diff --git a/target/mips/kvm.c b/target/mips/kvm.c
index 3ca3a0da93f..c511a1303c6 100644
--- a/target/mips/kvm.c
+++ b/target/mips/kvm.c
@@ -82,7 +82,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
}
}
- if (kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (kvm_mips_msa_cap && ase_msa_available(env)) {
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_MIPS_MSA, 0, 0);
if (ret < 0) {
/* mark unsupported so it gets disabled on reset */
@@ -108,7 +108,7 @@ void kvm_mips_reset_vcpu(MIPSCPU *cpu)
warn_report("KVM does not support FPU, disabling");
env->CP0_Config1 &= ~(1 << CP0C1_FP);
}
- if (!kvm_mips_msa_cap && env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (!kvm_mips_msa_cap && ase_msa_available(env)) {
warn_report("KVM does not support MSA, disabling");
env->CP0_Config3 &= ~(1 << CP0C3_MSAP);
}
@@ -621,7 +621,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int
level)
* FPU register state is a subset of MSA vector state, so don't put FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -640,7 +640,7 @@ static int kvm_mips_put_fpu_registers(CPUState *cs, int
level)
}
/* Only put MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
if (level == KVM_PUT_FULL_STATE) {
err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_MSA_IR,
@@ -701,7 +701,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
* FPU register state is a subset of MSA vector state, so don't save
FPU
* registers if we're emulating a CPU with MSA.
*/
- if (!(env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if (!ase_msa_available(env)) {
/* Floating point registers */
for (i = 0; i < 32; ++i) {
if (env->CP0_Status & (1 << CP0St_FR)) {
@@ -720,7 +720,7 @@ static int kvm_mips_get_fpu_registers(CPUState *cs)
}
/* Only get MSA state if we're emulating a CPU with MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
/* MSA Control Registers */
err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_MSA_IR,
&env->msair);
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 80c9c17819f..cb822e52c4b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24928,8 +24928,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
gen_trap(ctx, op1, rs, rt, -1);
break;
case OPC_LSA: /* OPC_PMON */
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
} else {
/* Pmon entry point, also R4010 selsl */
@@ -25031,8 +25030,7 @@ static void decode_opc_special(CPUMIPSState *env,
DisasContext *ctx)
}
break;
case OPC_DLSA:
- if ((ctx->insn_flags & ISA_MIPS32R6) ||
- (env->CP0_Config3 & (1 << CP0C3_MSAP))) {
+ if ((ctx->insn_flags & ISA_MIPS32R6) || ase_msa_available(env)) {
decode_opc_special_r6(env, ctx);
}
break;
@@ -31879,7 +31877,7 @@ void cpu_state_reset(CPUMIPSState *env)
}
/* MSA */
- if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
+ if (ase_msa_available(env)) {
msa_reset(env);
}
--
2.26.2
- [PATCH 00/17] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 01/17] target/mips: Introduce ase_msa_available() helper,
Philippe Mathieu-Daudé <=
- [PATCH 02/17] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 03/17] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 04/17] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 05/17] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 06/17] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 07/17] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 08/17] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 09/17] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 10/17] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07
- [PATCH 11/17] target/mips: Move msa_reset() to mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/07