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[PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim pr
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From: |
Alistair Francis |
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Subject: |
[PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process |
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Date: |
Thu, 17 Dec 2020 22:00:57 -0800 |
Previously if an interrupt occured during the claim process (after the
interrupt is claimed but before it's completed) it would never be
cleared.
This patch ensures that we also clear the hidden_pending bits as well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Jackie Ke <jackieke724@hotmail.com>
Message-id:
4e9786084a86f220689123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
---
hw/intc/ibex_plic.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index 341c9db405..c1b72fcab0 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -43,16 +43,23 @@ static void ibex_plic_irqs_set_pending(IbexPlicState *s,
int irq, bool level)
{
int pending_num = irq / 32;
+ if (!level) {
+ /*
+ * If the level is low make sure we clear the hidden_pending.
+ */
+ s->hidden_pending[pending_num] &= ~(1 << (irq % 32));
+ }
+
if (s->claimed[pending_num] & 1 << (irq % 32)) {
/*
* The interrupt has been claimed, but not completed.
* The pending bit can't be set.
+ * Save the pending level for after the interrupt is completed.
*/
s->hidden_pending[pending_num] |= level << (irq % 32);
- return;
+ } else {
+ s->pending[pending_num] |= level << (irq % 32);
}
-
- s->pending[pending_num] |= level << (irq % 32);
}
static bool ibex_plic_irqs_pending(IbexPlicState *s, uint32_t context)
--
2.29.2
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2020/12/18
- [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB, Alistair Francis, 2020/12/18
- [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash, Alistair Francis, 2020/12/18
- [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV, Alistair Francis, 2020/12/18
- [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR, Alistair Francis, 2020/12/18
- [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format, Alistair Francis, 2020/12/18
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/18
- [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/18
- [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process,
Alistair Francis <=
- [PULL 09/23] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 10/23] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/18
- [PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/18
- [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 17/23] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/18