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[PULL 10/23] riscv: virt: Remove target macro conditionals
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From: |
Alistair Francis |
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Subject: |
[PULL 10/23] riscv: virt: Remove target macro conditionals |
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Date: |
Thu, 17 Dec 2020 22:01:01 -0800 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id:
aed1174c2efd2f050fa5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
---
include/hw/riscv/virt.h | 6 ------
hw/riscv/virt.c | 2 +-
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index b4ed9a32eb..84b7a3848f 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -89,10 +89,4 @@ enum {
#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
-#if defined(TARGET_RISCV32)
-#define VIRT_CPU TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-#define VIRT_CPU TYPE_RISCV_CPU_BASE64
-#endif
-
#endif
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 3cc18a76e7..3e41dbfd3c 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -704,7 +704,7 @@ static void virt_machine_class_init(ObjectClass *oc, void
*data)
mc->desc = "RISC-V VirtIO board";
mc->init = virt_machine_init;
mc->max_cpus = VIRT_CPUS_MAX;
- mc->default_cpu_type = VIRT_CPU;
+ mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
mc->pci_allow_0_address = true;
mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
--
2.29.2
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2020/12/18
- [PULL 01/23] hw/riscv: sifive_u: Add UART1 DT node in the generated DTB, Alistair Francis, 2020/12/18
- [PULL 02/23] hw/riscv: microchip_pfsoc: add QSPI NOR flash, Alistair Francis, 2020/12/18
- [PULL 04/23] target/riscv: Fix the bug of HLVX/HLV/HSV, Alistair Francis, 2020/12/18
- [PULL 05/23] target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR, Alistair Francis, 2020/12/18
- [PULL 03/23] hw/core/register.c: Don't use '#' flag of printf format, Alistair Francis, 2020/12/18
- [PULL 07/23] hw/riscv: Expand the is 32-bit check to support more CPUs, Alistair Francis, 2020/12/18
- [PULL 08/23] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/18
- [PULL 06/23] intc/ibex_plic: Clear interrupts that occur during claim process, Alistair Francis, 2020/12/18
- [PULL 09/23] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/18
- [PULL 10/23] riscv: virt: Remove target macro conditionals,
Alistair Francis <=
- [PULL 11/23] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 12/23] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 14/23] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 15/23] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/18
- [PULL 13/23] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 16/23] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/18
- [PULL 18/23] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 17/23] target/riscv: Specify the XLEN for CPUs, Alistair Francis, 2020/12/18
- [PULL 20/23] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/18
- [PULL 19/23] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/18