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[RFC PATCH v2 01/32] Temp: Add the PCI_EXT_ID_DVSEC definition to the qe
From: |
Ben Widawsky |
Subject: |
[RFC PATCH v2 01/32] Temp: Add the PCI_EXT_ID_DVSEC definition to the qemu pci_regs.h copy. |
Date: |
Tue, 5 Jan 2021 08:52:52 -0800 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This hasn't yet been added to the linux kernel tree, so for purposes
of this RFC just add it locally.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
include/standard-headers/linux/pci_regs.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/standard-headers/linux/pci_regs.h
b/include/standard-headers/linux/pci_regs.h
index a95d55f9f2..5d0b79b9da 100644
--- a/include/standard-headers/linux/pci_regs.h
+++ b/include/standard-headers/linux/pci_regs.h
@@ -723,6 +723,7 @@
#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
+#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */
#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */
#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */
#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
--
2.30.0
- [RFC PATCH v2 00/32] CXL 2.0 Support, Ben Widawsky, 2021/01/05
- [RFC PATCH v2 01/32] Temp: Add the PCI_EXT_ID_DVSEC definition to the qemu pci_regs.h copy.,
Ben Widawsky <=
- [RFC PATCH v2 02/32] hw/pci/cxl: Add a CXL component type (interface), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 03/32] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 04/32] hw/cxl/device: Introduce a CXL device (8.2.8), Ben Widawsky, 2021/01/05
- [RFC PATCH v2 05/32] hw/cxl/device: Implement the CAP array (8.2.8.1-2), Ben Widawsky, 2021/01/05
[RFC PATCH v2 06/32] hw/cxl/device: Add device status (8.2.8.3), Ben Widawsky, 2021/01/05
[RFC PATCH v2 07/32] hw/cxl/device: Implement basic mailbox (8.2.8.4), Ben Widawsky, 2021/01/05