[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PULL 23/35] hw/intc: Rework Loongson LIOINTC

From: Peter Maydell
Subject: Re: [PULL 23/35] hw/intc: Rework Loongson LIOINTC
Date: Mon, 11 Jan 2021 10:35:01 +0000

On Mon, 11 Jan 2021 at 10:20, BALATON Zoltan <balaton@eik.bme.hu> wrote:
> On Mon, 11 Jan 2021, Jiaxun Yang wrote:
> > On Mon, Jan 11, 2021, at 8:36 AM, Huacai Chen wrote:
> >> I think R_END should be 0x60, Jiaxun, what do you think?
> >
> > U r right.
> > The manual is misleading.
> The R_END constant is also used in loongson_liointc_init() for the length
> of the memory region so you might want to revise that. If this is a 32 bit
> register then you should decide what R_END means? Is it the end of the
> memory region in which case the reg starts at R_END - 4 or is it the
> address of the last reg in which case the memory region ends at R_END + 4.
> From the above I think it's the address of the last reg so you'll probably
> need to add 4 in loongson_liointc_init() when creating the memory region.

Mmm, or check
  (addr >= R_START && addr < (R_START + R_ISR_SIZE * NUM_CORES))

Side note: R_ISR_SIZE is 8, but the code makes both the
32-bit addresses you can read/write in that 8-byte range
behave the same way. Is that really what the hardware does ?
Or does it actually have 1 32-bit register per core, spaced
8 bytes apart ?

-- PMM

reply via email to

[Prev in Thread] Current Thread [Next in Thread]