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Re: [PULL 23/35] hw/intc: Rework Loongson LIOINTC

From: Jiaxun Yang
Subject: Re: [PULL 23/35] hw/intc: Rework Loongson LIOINTC
Date: Tue, 12 Jan 2021 08:35:21 +0800
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.6.0

在 2021/1/11 下午6:35, Peter Maydell 写道:
On Mon, 11 Jan 2021 at 10:20, BALATON Zoltan <balaton@eik.bme.hu> wrote:
On Mon, 11 Jan 2021, Jiaxun Yang wrote:
On Mon, Jan 11, 2021, at 8:36 AM, Huacai Chen wrote:
I think R_END should be 0x60, Jiaxun, what do you think?
U r right.
The manual is misleading.
The R_END constant is also used in loongson_liointc_init() for the length
of the memory region so you might want to revise that. If this is a 32 bit
register then you should decide what R_END means? Is it the end of the
memory region in which case the reg starts at R_END - 4 or is it the
address of the last reg in which case the memory region ends at R_END + 4.
 From the above I think it's the address of the last reg so you'll probably
need to add 4 in loongson_liointc_init() when creating the memory region.
Mmm, or check
   (addr >= R_START && addr < (R_START + R_ISR_SIZE * NUM_CORES))

Side note: R_ISR_SIZE is 8, but the code makes both the
32-bit addresses you can read/write in that 8-byte range
behave the same way. Is that really what the hardware does ?
Or does it actually have 1 32-bit register per core, spaced
8 bytes apart ?

Yes, the hardware was designed like that. It have 1 32-bit register
per core but spaced 8 bytes apart.

I assume they were planing to add more ISRs in the future but as the
product line have been ceased I'm not going to handle that.

I'll send a patch for fix.


- Jiaxun

-- PMM

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