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[PULL 24/46] tcg/tci: Implement 64-bit division
From: |
Richard Henderson |
Subject: |
[PULL 24/46] tcg/tci: Implement 64-bit division |
Date: |
Fri, 5 Feb 2021 12:56:28 -1000 |
Trivially implemented like other arithmetic.
Tested via check-tcg and the ppc64 target.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tci/tcg-target.h | 4 ++--
tcg/tci.c | 28 ++++++++++++++++++++++------
tcg/tci/tcg-target.c.inc | 10 ++++------
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
index bb784e018e..7fc349a3de 100644
--- a/tcg/tci/tcg-target.h
+++ b/tcg/tci/tcg-target.h
@@ -100,8 +100,8 @@
#define TCG_TARGET_HAS_extract_i64 0
#define TCG_TARGET_HAS_sextract_i64 0
#define TCG_TARGET_HAS_extract2_i64 0
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
diff --git a/tcg/tci.c b/tcg/tci.c
index 25329345cf..5c84a1c979 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -894,14 +894,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState
*env,
t2 = tci_read_ri64(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2);
break;
-#if TCG_TARGET_HAS_div_i64
case INDEX_op_div_i64:
- case INDEX_op_divu_i64:
- case INDEX_op_rem_i64:
- case INDEX_op_remu_i64:
- TODO();
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
+ break;
+ case INDEX_op_divu_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
+ break;
+ case INDEX_op_rem_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
+ break;
+ case INDEX_op_remu_i64:
+ t0 = *tb_ptr++;
+ t1 = tci_read_ri64(regs, &tb_ptr);
+ t2 = tci_read_ri64(regs, &tb_ptr);
+ tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break;
-#endif
case INDEX_op_and_i64:
t0 = *tb_ptr++;
t1 = tci_read_ri64(regs, &tb_ptr);
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 6dc5bac2f3..3327ce3072 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -577,6 +577,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
case INDEX_op_sar_i64:
case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
+ case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
+ case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
tcg_out_r(s, args[0]);
tcg_out_ri64(s, const_args[1], args[1]);
tcg_out_ri64(s, const_args[2], args[2]);
@@ -590,12 +594,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
tcg_debug_assert(args[4] <= UINT8_MAX);
tcg_out8(s, args[4]);
break;
- case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
- TODO();
- break;
case INDEX_op_brcond_i64:
tcg_out_r(s, args[0]);
tcg_out_ri64(s, const_args[1], args[1]);
--
2.25.1
- [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}, (continued)
- [PULL 21/46] tcg/tci: Merge INDEX_op_{st_i32,st32_i64}, Richard Henderson, 2021/02/05
- [PULL 20/46] tcg/tci: Move stack bounds check to compile-time, Richard Henderson, 2021/02/05
- [PULL 22/46] tcg/tci: Use g_assert_not_reached, Richard Henderson, 2021/02/05
- [PULL 23/46] tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*, Richard Henderson, 2021/02/05
- [PULL 26/46] tcg/tci: Restrict TCG_TARGET_NB_REGS to 16, Richard Henderson, 2021/02/05
- [PULL 28/46] tcg/tci: Remove TCG_CONST, Richard Henderson, 2021/02/05
- [PULL 25/46] tcg/tci: Remove TODO as unused, Richard Henderson, 2021/02/05
- [PULL 32/46] cpu: Move synchronize_from_tb() to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 29/46] cpu: Introduce TCGCpuOperations struct, Richard Henderson, 2021/02/05
- [PULL 27/46] tcg/tci: Fix TCG_REG_R4 misusage, Richard Henderson, 2021/02/05
- [PULL 24/46] tcg/tci: Implement 64-bit division,
Richard Henderson <=
- [PULL 30/46] target/riscv: remove CONFIG_TCG, as it is always TCG, Richard Henderson, 2021/02/05
- [PULL 31/46] accel/tcg: split TCG-only code from cpu_exec_realizefn, Richard Henderson, 2021/02/05
- [PULL 33/46] cpu: Move cpu_exec_* to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 34/46] cpu: Move tlb_fill to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 35/46] cpu: Move debug_excp_handler to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 36/46] target/arm: do not use cc->do_interrupt for KVM directly, Richard Henderson, 2021/02/05
- [PULL 38/46] cpu: move cc->transaction_failed to tcg_ops, Richard Henderson, 2021/02/05
- [PULL 39/46] cpu: move do_unaligned_access to tcg_ops, Richard Henderson, 2021/02/05