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[RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleav
From: |
Philippe Mathieu-Daudé |
Subject: |
[RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword) |
Date: |
Sun, 14 Feb 2021 18:58:52 +0100 |
Introduce the PINTEH opcode (Parallel Interleave Even Halfword).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tx79.decode | 1 +
target/mips/tx79_translate.c | 45 ++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/target/mips/tx79.decode b/target/mips/tx79.decode
index 653910371d2..fbd2be569ad 100644
--- a/target/mips/tx79.decode
+++ b/target/mips/tx79.decode
@@ -57,6 +57,7 @@ PXOR 011100 ..... ..... ..... 10011 001001
@rs_rt_rd
# MMI3
+PINTEH 011100 ..... ..... ..... 01010 101001 @rs_rt_rd
PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd
POR 011100 ..... ..... ..... 10010 101001 @rs_rt_rd
PNOR 011100 ..... ..... ..... 10011 101001 @rs_rt_rd
diff --git a/target/mips/tx79_translate.c b/target/mips/tx79_translate.c
index ac75d95b82b..47d84c465a2 100644
--- a/target/mips/tx79_translate.c
+++ b/target/mips/tx79_translate.c
@@ -638,3 +638,48 @@ static bool trans_PCPYUD(DisasContext *s, arg_rtype *a)
return true;
}
+
+/* Parallel Interleave Even Halfword */
+static bool trans_PINTEH(DisasContext *ctx, arg_rtype *a)
+{
+ TCGv_i64 ax, bx;
+
+ if (a->rd == 0) {
+ /* nop */
+ return true;
+ }
+
+ if (unlikely(a->rs == 0 && a->rt == 0)) {
+ tcg_gen_movi_i64(cpu_gpr[a->rd], 0);
+ tcg_gen_movi_i64(cpu_gpr_hi[a->rd], 0);
+ return true;
+ }
+
+ ax = tcg_temp_new_i64();
+ bx = tcg_temp_new_i64();
+
+ /* Lower halve */
+ gen_load_gpr(ax, a->rs);
+ gen_load_gpr(bx, a->rt);
+ if (a->rd != a->rt) {
+ tcg_gen_mov_i64(cpu_gpr[a->rd], bx);
+ }
+ tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 16, 16);
+ tcg_gen_shri_i64(ax, ax, 32);
+ tcg_gen_deposit_i64(cpu_gpr[a->rd], cpu_gpr[a->rd], ax, 48, 16);
+
+ /* Upper halve */
+ gen_load_gpr_hi(ax, a->rs);
+ gen_load_gpr_hi(bx, a->rt);
+ if (a->rd != a->rt) {
+ tcg_gen_mov_i64(cpu_gpr_hi[a->rd], bx);
+ }
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 16, 16);
+ tcg_gen_shri_i64(ax, ax, 32);
+ tcg_gen_deposit_i64(cpu_gpr_hi[a->rd], cpu_gpr_hi[a->rd], ax, 48, 16);
+
+ tcg_temp_free(bx);
+ tcg_temp_free(ax);
+
+ return true;
+}
--
2.26.2
- Re: [RFC PATCH 14/42] target/mips/tx79: Salvage instructions description comment, (continued)
- [RFC PATCH 16/42] target/mips/tx79: Introduce PSUB* opcodes (Parallel Subtract), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 19/42] target/mips/tx79: Introduce PCEQ* opcodes (Parallel Compare for Equal), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 18/42] target/mips/tx79: Introduce PEXTU[BHW] opcodes (Parallel Extend Lower), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 20/42] target/mips/tx79: Introduce PCGT* (Parallel Compare for Greater Than), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 21/42] target/mips/tx79: Introduce PPACW opcode (Parallel Pack to Word), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 22/42] target/mips/tx79: Introduce PINTEH (Parallel Interleave Even Halfword),
Philippe Mathieu-Daudé <=
- [RFC PATCH 23/42] target/mips/tx79: Introduce PEXE[HW] opcodes (Parallel Exchange Even), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 24/42] target/mips/tx79: Introduce PROT3W opcode (Parallel Rotate 3 Words), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 25/42] target/mips/tx79: Introduce LQ opcode (Load Quadword), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 26/42] target/mips/tx79: Introduce SQ opcode (Store Quadword), Philippe Mathieu-Daudé, 2021/02/14
- [RFC PATCH 27/42] target/mips/translate: Make gen_rdhwr() public, Philippe Mathieu-Daudé, 2021/02/14