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[PATCH 32/44] hw/arm/armsse: Add support for SSE variants with a system
From: |
Peter Maydell |
Subject: |
[PATCH 32/44] hw/arm/armsse: Add support for SSE variants with a system counter |
Date: |
Fri, 19 Feb 2021 14:46:05 +0000 |
The SSE-300 has a system counter device; add support for SSE
variants having this device.
As with the existing devices like the cache control block, CPUID
block, etc, we don't try to make the MMIO addresses configurable. We
can do that if and when we need to model a future SSE variant which
has the counter in a different location.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/armsse.h | 3 +++
hw/arm/armsse.c | 27 +++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 104ba8d26ec..149f17dfc88 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -97,6 +97,7 @@
#include "hw/misc/tz-mpc.h"
#include "hw/timer/cmsdk-apb-timer.h"
#include "hw/timer/cmsdk-apb-dualtimer.h"
+#include "hw/timer/sse-counter.h"
#include "hw/watchdog/cmsdk-apb-watchdog.h"
#include "hw/misc/iotkit-sysctl.h"
#include "hw/misc/iotkit-sysinfo.h"
@@ -164,6 +165,8 @@ struct ARMSSE {
CMSDKAPBWatchdog cmsdk_watchdog[3];
+ SSECounter sse_counter;
+
IoTKitSysCtl sysctl;
IoTKitSysCtl sysinfo;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index b316fe69571..4387e98376c 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -66,6 +66,7 @@ struct ARMSSEInfo {
bool has_cachectrl;
bool has_cpusecctrl;
bool has_cpuid;
+ bool has_sse_counter;
Property *props;
const ARMSSEDeviceInfo *devinfo;
const bool *irq_is_common;
@@ -363,6 +364,7 @@ static const ARMSSEInfo armsse_variants[] = {
.has_cachectrl = false,
.has_cpusecctrl = false,
.has_cpuid = false,
+ .has_sse_counter = false,
.props = iotkit_properties,
.devinfo = iotkit_devices,
.irq_is_common = sse200_irq_is_common,
@@ -379,6 +381,7 @@ static const ARMSSEInfo armsse_variants[] = {
.has_cachectrl = true,
.has_cpusecctrl = true,
.has_cpuid = true,
+ .has_sse_counter = false,
.props = armsse_properties,
.devinfo = sse200_devices,
.irq_is_common = sse200_irq_is_common,
@@ -652,6 +655,11 @@ static void armsse_init(Object *obj)
g_free(name);
}
}
+ if (info->has_sse_counter) {
+ object_initialize_child(obj, "sse-counter", &s->sse_counter,
+ TYPE_SSE_COUNTER);
+ }
+
object_initialize_child(obj, "nmi-orgate", &s->nmi_orgate, TYPE_OR_IRQ);
object_initialize_child(obj, "ppc-irq-orgate", &s->ppc_irq_orgate,
TYPE_OR_IRQ);
@@ -1000,6 +1008,25 @@ static void armsse_realize(DeviceState *dev, Error
**errp)
qdev_connect_gpio_out(DEVICE(&s->nmi_orgate), 0,
qdev_get_gpio_in_named(DEVICE(&s->armv7m), "NMI",
0));
+ /* The SSE-300 has a System Counter / System Timestamp Generator */
+ if (info->has_sse_counter) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->sse_counter);
+
+ qdev_connect_clock_in(DEVICE(sbd), "CLK", s->mainclk);
+ if (!sysbus_realize(sbd, errp)) {
+ return;
+ }
+ /*
+ * The control frame is only in the Secure region;
+ * the status frame is in the NS region (and visible in the
+ * S region via the alias mapping).
+ */
+ memory_region_add_subregion(&s->container, 0x58100000,
+ sysbus_mmio_get_region(sbd, 0));
+ memory_region_add_subregion(&s->container, 0x48101000,
+ sysbus_mmio_get_region(sbd, 1));
+ }
+
/* Devices behind APB PPC0:
* 0x40000000: timer0
* 0x40001000: timer1
--
2.20.1
- [PATCH 25/44] hw/arm/armsse: Move watchdogs into data-driven framework, (continued)
- [PATCH 25/44] hw/arm/armsse: Move watchdogs into data-driven framework, Peter Maydell, 2021/02/19
- [PATCH 37/44] hw/misc/mps2-fpgaio: Fold counters subsection into main vmstate, Peter Maydell, 2021/02/19
- [PATCH 38/44] hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register, Peter Maydell, 2021/02/19
- [PATCH 41/44] hw/arm/mps2-tz: Make initsvtor0 setting board-specific, Peter Maydell, 2021/02/19
- [PATCH 40/44] hw/arm/mps2-tz: Support running APB peripherals on different clock, Peter Maydell, 2021/02/19
- [PATCH 35/44] hw/arm/armsse: Add SSE-300 support, Peter Maydell, 2021/02/19
- [PATCH 28/44] hw/arm/armsse: Move sysctl register block into data-driven framework, Peter Maydell, 2021/02/19
- [PATCH 27/44] hw/arm/armsse: Move sysinfo register block into data-driven framework, Peter Maydell, 2021/02/19
- [PATCH 30/44] hw/arm/armsse: Add missing SSE-200 SYS_PPU, Peter Maydell, 2021/02/19
- [PATCH 29/44] hw/arm/armsse: Move PPUs into data-driven framework, Peter Maydell, 2021/02/19
- [PATCH 32/44] hw/arm/armsse: Add support for SSE variants with a system counter,
Peter Maydell <=
- [PATCH 36/44] hw/arm/mps2-tz: Make UART overflow IRQ board-specific, Peter Maydell, 2021/02/19
- [PATCH 39/44] hw/misc/mps2-scc: Implement changes for AN547, Peter Maydell, 2021/02/19
- [PATCH 42/44] hw/arm/mps2-tz: Add new mps3-an547 board, Peter Maydell, 2021/02/19
- [PATCH 44/44] tests/qtest/sse-timer-test: Add simple tests of the SSE timer and counter, Peter Maydell, 2021/02/19
- [PATCH 43/44] docs/system/arm/mps2.rst: Document the new mps3-an547 board, Peter Maydell, 2021/02/19
- Re: [PATCH 00/44] hw/arm: New board model mps3-an547, no-reply, 2021/02/19